ICS848004I [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL - TO- SSTL_2频率合成器
| 型号： | ICS848004I |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-SSTL_2 FREQUENCY SYNTHESIZER |
| 文件： | 总11页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS848004I is a 4 output SSTL_2
• Four SSTL_2 differential clock output pairs
ICS
Synthesizer optimized to generate Fibre
Channel reference clock frequencies and is
a member of the HiPerClocksTM family of high
performance clock solutions from ICS. Using
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
HiPerClockS™
• Supports the following output frequencies: 212.5MHz,
a 26.5625MHz 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz.
The ICS848004I uses ICS’ 3rd generation low phase
noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel
jitter requirements. The ICS848004I is packaged in a
small 24-pin TSSOP package.
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.80ps (typical)
• SSTL operating voltage supply ranges:
VDD = 3.0V to 3.6V, VDDO = 3.0V to 3.6V
V
V
DD = 2.3V to 3.6V, VDDO = 2.3V to 2.7V
DD = 2.3V to 3.6V, VDDO = 1.7V to 1.9V
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Output
Frequency
(MHz)
nQ1
Q1
1
24
23
22
nQ2
Input
M Divider N Divider M/N Divider
Value
2
Q2
Frequency F_SEL1 F_SEL0
(MHz)
3
4
VDDo
Q0
VDDO
Q3
Value
Value
21
20
19
18
17
16
15
14
13
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
0
0
1
1
0
0
0
1
0
1
1
0
24
24
24
24
24
24
3
4
8
6
4
2
6
8
212.5
159.375
106.25
53.125
156.25
187.5
5
6
7
8
nQ0
MR
nPLL_SEL
nc
nQ3
GND
nc
6
nXTAL_SEL
9
VDDA
TEST_CLK
GND
XTAL_IN
XTAL_OUT
12
4
10
11
12
F_SEL0
VDD
F_SEL1
3
ICS848004I
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
BLOCK DIAGRAM
Pulldown
2
F_SEL[1:0]
G Package
TopView
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
0 0 ÷3
nQ0
Pulldown
TEST_CLK
1
0
1
0
0 1 ÷4
Q1
26.5625MHz
XTAL_IN
1 0 ÷6
VCO
637.5MHz
(w/26.5625MHz
Reference)
1 1 ÷12
nQ1
Phase
Detector
OSC
XTAL_OUT
Q2
Pulldown
nXTAL_SEL
nQ2
M = 24 (fixed)
Q3
nQ3
Pulldown
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
848004AGI
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REV.A AUGUST 18, 2005
1
PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VDDO
Type
Output
Description
Differential output pair. SSTL_2 interface levels.
Output supply pins.
3, 22
4, 5
Power
Ouput
Q0, nQ0
Differential output pair. SSTL_2 interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
7
nPLL_SEL
Input
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
9
nc
Unused
Power
No connect.
VDDA
Analog supply pin.
F_SEL0,
F_SEL1
10, 12
11
Input
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VDD
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
13, 14
15, 19
16
GND
Power
Input
Power supply ground.
TEST_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. SSTL_2 interface levels.
Differential output pair. SSTL_2 interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
58.3°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.0
3.0
3.0
3.3
3.3
3.6
3.6
3.6
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.3
V
TBD
TBD
TBD
mA
mA
mA
IDDA
IDDO
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ OR 2.5V 10ꢀ, VDDO = 2.5V 10ꢀ,
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.3
2.3
2.3
3.0
3.0
3.6
3.6
2.7
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.5
V
TBD
TBD
TBD
mA
mA
mA
IDDA
IDDO
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ OR 2.5V 10ꢀ, VDDO = 1.8V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.3
2.3
1.7
3.0
3.0
3.6
3.6
1.9
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
1.8
V
TBD
TBD
TBD
mA
mA
mA
IDDA
IDDO
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REV.A AUGUST 18, 2005
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
VDD = 2.5V
1.7
-0.3
-0.3
V
DD = 3.3V
VDD = 2.5V
0.7
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
Input
High Current
IIH
VDD = VIN = 3.6 or 2.7V
150
µA
µA
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
VDD = 3.6V or 2.7V,
Input
Low Current
IIL
-150
V
IN = 0V
TABLE 3E. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD
VPP
Output Differential Voltage
0.7
0.15
0.5
V
V
V
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
1.3
VCMR
VOH
VOL
VDDO - 0.85
>2.1
<0.9
Output Low Voltage; NOTE 2
NOTE 1: VCMR, VPP defined for driving TEST_CLK input with differential levels other than SSTL_2.
NOTE 2: Outputs terminated with 50Ω to ground.
TABLE 3F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ OR 2.5V 10ꢀ, VDDO = 2.5V 10ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD
VPP
Output Differential Voltage
0.7
0.15
0.5
V
V
V
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
1.3
VCMR
VOH
VOL
VDDO - 0.85
>1.77
<0.73
Output Low Voltage; NOTE 2
NOTE 1: VCMR, VPP defined for driving TEST_CLK input with differential levels other than SSTL_2.
NOTE 2: Outputs terminated with 50Ω to ground.
TABLE 3G. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V 10ꢀ OR 2.5V 10ꢀ, VDDO = 1.8V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD
VPP
Output Differential Voltage
0.7
0.15
0.5
V
V
V
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
1.3
VCMR
VOH
VOL
VDDO - 0.85
>1.19
Output Low Voltage; NOTE 2
<0.615
NOTE 1: VCMR, VPP defined for driving TEST_CLK input with differential levels other than SSTL_2.
NOTE 2: Outputs terminated with 50Ω to ground.
848004AGI
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4
PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
23.33
28.33
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 5. AC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
186.67
140
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
tsk(o)
Output Skew; NOTE 1, 2
TBD
0.80
0.78
0.50
0.81
0.79
650
50
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
156.25MHz, (1.875MHz - 20MHz)
106.25MHz, (637kHz - 10MHz)
53.125MHz, (637kHz - 10MHz)
20ꢀ to 80ꢀ
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
+1.65V +/- 10ꢀ
+1.65V +/- 10ꢀ
+1.25V +/- 10ꢀ
+1.25V +/- 10ꢀ
SCOPE
SCOPE
Zo = 50 Ohm
Zo = 50 Ohm
VDD VDDO
50 Ohm
VDD VDDO
50 Ohm
SSTL
Driv er
SSTL
Driv er
GND
GND
50 Ohm
50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
-1.65V +/- 10ꢀ
-1.25V +/- 10ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQx
Qx
Phase Noise Mask
nQy
Qy
Offset Frequency
tsk(o)
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT SKEW
RMS PHASE JITTER
nQ0:nQ3
Q0:Q3
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Pulse Width
Clock
Outputs
tPERIOD
20ꢀ
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV.A AUGUST 18, 2005
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS848004I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS848004I has been characterized with 18pF parallel reso- were determined using a 26.5625MHz 18pF parallel resonant
nant crystals. The capacitor values shown in Figure 2 below crystal and were chosen to minimize the ppm error.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
ICS848004I
Figure 2. CRYSTAL INPUt INTERFACE
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REV.A AUGUST 18, 2005
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
SSTL INTERFACE
Figures 3A to 3C show interface example of ICS848004I
SOCKET/nSOCKET input driven by an SSTL driver.The input
interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements.The SSTL termination shown in these
examples are also suitable for ICS48004I SSTL output drivers.
2.5V
1.25V
2.5V
2.5V
R3
R4
2.5V
120
120
R1
60
R2
60
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
SOCKET_CLK
nSOCKET_CLK
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
SOCKET_CLK
nSOCKET_CLK
R1
120
R2
120
FIGURE 3B. SSTL INTERFACE FOR VDD/2 = 1.25V
WITH NO AVAILABLE
FIGURE 3A.TYPICAL SSTL INTERFACE FOR VDD/2 = 1.25V
BEING AVAILABLE
2.5V
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
SOCKET_CLK
nSOCKET_CLK
R1
R2
25
25
R3
120
FIGURE 3C.DIFFERENTIAL SSTL INTERFACE
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REV.A AUGUST 18, 2005
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS848004I is: 2951
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PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV.A AUGUST 18, 2005
10
PRELIMINARY
ICS848004I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
SSTL_2 FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS848004AGI
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
ICS848004AGI
ICS848004AGI
24 Lead TSSOP
24 Lead TSSOP
ICS848004AGIT
2500 tape & reel
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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REV.A AUGUST 18, 2005
11
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