ICS8516FY [ICSI]
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP; 低偏移， 1至16差分至LVDS时钟分配芯片
| 型号： | ICS8516FY |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP |
| 文件： | 总13页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
GENERAL DESCRIPTION
FEATURES
The ICS8516 is a low skew, high performance • 16 Differential LVDS outputs
ICS
1-to-16 Differential-to-LVDS Clock Distribution
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
HiPerClockS™
Chip and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8516 CLK, nCLK pair can accept
• Maximum output frequency: 700MHz
any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the ICS8516 provides a low power, low noise, point-
to-point solution for distributing clock signals over controlled
impedances of 100Ω.
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
Dual output enable inputs allow the ICS8516 to be used in a
1-to-16 or 1-to-8 input/output mode.
• Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
• LVDS compatible
• Output skew: 90ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
48 47 46 45 44 43 42 41 40 39 38 37
V
DD
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
Q0
Q15
nQ5
Q5
2
nQ10
Q10
nQ0
nQ15
3
Q1
nQ1
Q14
nQ14
nQ4
Q4
4
nQ11
Q11
5
Q2
nQ2
Q13
nQ13
V
DD
6
V
DD
ICS8516
GND
nQ3
Q3
7
GND
nQ12
Q12
8
Q12
nQ12
Q3
nQ3
9
nQ2
Q2
10
11
12
nQ13
Q13
Q11
nQ11
Q4
nQ4
V
DD
V
DD
13 14 15 16 17 18 19 20 21 22 23 24
Q10
nQ10
Q5
nQ5
Q9
nQ9
Q6
nQ6
Q8
nQ8
Q7
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
nQ7
OE1
OE2
TopView
8516FY
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REV. A JULY 30, 2004
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
TABLE 1. PIN DESCRIPTIONS
Number
1, 6, 12,
25, 31, 36
Name
Type
Description
Positive supply pins.
VDD
Power
2, 3
4, 5
nQ5, Q5
nQ4, Q4
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7, 17, 20,
30, 41, 44
GND
Power
Power supply ground.
8, 9
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
Output
Output
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
10, 11
13, 14
15, 16
18
Pullup
19
CLK
Input
Pulldown Non-inverting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
21, 22
23, 24
26, 27
28, 29
32, 33
34, 35
37, 38
39, 40
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Q11, nQ11
Q10, nQ10
Q9, nQ9
Q8, nQ8
Output
Output
Output
Output
Output
Output
Output
Output
Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15;
OE1 controls outputs Q0, nQ0 thru Q7, nQ7.
LVCMOS/LVTTL interface levels.
42, 43
OE2, OE1
Input
Pullup
45, 46
47, 48
nQ7, Q7
nQ6, Q6
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8516FY
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
CPD
4
pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
OE1
OE2
Q0:Q7
Hi Z
nQ0:nQ7
Hi Z
Q8:Q15
nQ8:nQ15
Hi Z
0
1
0
1
0
0
1
1
Hi Z
Hi Z
ACTIVE
Hi Z
ACTIVE
Hi Z
Hi Z
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
nQ0:nQ15
Input to Output Mode
Polarity
CLK
nCLK
Q0:Q15
LOW
0
1
0
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
HIGH
LOW
0
Biased; NOTE 1
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8516FY
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REV. A JULY 30, 2004
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Inputs, VI
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
Outputs, VO
PackageThermal Impedance, θJA 47.9°C/W (0 lfpm)
StorageTemperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
VDD Positive Supply Voltage
Test Conditions
Minimum Typical Maximum Units
3.135
3.3
135
60
3.465
165
75
V
RL = 100Ω
mA
mA
IDD
Static Power Supply Current
No Load
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage OE1, OE2
2
VDD + 0.3
V
V
Input Low Voltage OE1, OE2
Input High Current OE1, OE2
Input Low Current OE1, OE2
-0.3
0.8
5
VDD = VIN = 3.465V
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum
Typical
Maximum Units
CLK
150
5
µA
µA
µA
µA
V
IIH Input High Current
nCLK
CLK
-5
IIL
Input Low Current
nCLK
-150
0.15
VPP
Peak-to-Peak Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined ast VIH.
8516FY
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
VOD
∆ VOD
VOS
Differential Output Voltage
250
400
600
50
mV
mV
V
VOD Magnitude Change
Offset Voltage
1.125
1.4
1.6
50
∆ VOS
IOZ
VOS Magnitude Change
mV
µA
µA
mA
mA
High Impedance Leakage Current
Power Off Leakage
-10
-1
+10
+1
IOFF
IOSD
Differential Output Short Circuit Current
Output Short Circuit Current
-5.5
-12
IOS/IOSB
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
2.4
90
500
550
55
5
MHz
ns
ps
ps
ps
ꢀ
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
1.6
2.0
tsk(o)
tsk(pp)
tR/tF
20ꢀ to 80ꢀ
100
45
odc
Output Duty Cycle
50
t
PZL, tPZH
PLZ, tPHZ
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
t
5
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8516FY
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REV. A JULY 30, 2004
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V 5ꢀ
SCOPE
nCLK
CLK
Qx
Power Supply
Float GND
VPP
VCMR
Cross Points
LVDS
+
-
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
nQ
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK
CLK
80ꢀ
tF
80ꢀ
VOD
Clock
20ꢀ
20ꢀ
nQ0:nQ15
Outputs
tR
Q0:Q15
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
8516FY
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ICS8516
Integrated
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Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
VDD
nQ0:nQ15
Q0:Q15
out
Pulse Width
➤
DC Input
LVDS
tPERIOD
tPW
out
VOS/∆ VOS
odc =
➤
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OFFSET VOLTAGE SETUP
VDD
VDD
➤
out
out
out
out
IOSD
LVDS
DC Input
100
V
OD/∆ VOD
DC Input
LVDS
➤
DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
VDD
out
IOS
DC Input
LVDS
LVDS
VDD
IOSB
out
IOFF
OUTPUT SHORT CIRCUIT CURRENT SETUP
POWER OFF LEAKAGE SETUP
8516FY
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ICS8516
Integrated
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Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
3.3V
Zo = 50 Ohm
LVDS_Driver
CLK
R1
100
nCLK
HiPerClockS
Zo = 50 Ohm
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
8516FY
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
8516FY
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of ICS8516. In this ex- integrity.The decoupling capacitors should be physically located
ample, the input is driven by an LVDS driver.For LVDS buffer, it is near the power pin.
recommended to terminate the unused outputs for better signal
Zo = 50 Ohm
+
R16
100
VDD=3.3V
-
Zo = 50 Ohm
LVDS_input
U1
8516
Zo = 50 Ohm
Zo = 50 Ohm
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
nQ1
Q1
nQ0
Q0
GND
nCLK
CLK
GND
Q15
nQ15
Q14
nQ14
Q6
nQ6
Q7
nQ7
GND
OE1
OE2
GND
nQ8
Q8
+
-
R10
100
LVDS_Driver
Zo = 50 Ohm
LVDS_input
R17
100
nQ9
Q9
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R1
100
Zo = 50 Ohm
LVDS_input
(U1-1)
(U1-6)
(U1-12)
(U1-25)
(U1-31)
(U1-36)
VDD=3.3V
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C5
0.1u
C6
0.1u
Decoupling capacitors located near the power pins
FIGURE 4. ICS8516 LVDS BUFFER SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8516 is: 1821
8516FY
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L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
8516FY
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REV. A JULY 30, 2004
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8516FY
Marking
ICS8516FY
ICS8516FY
ICS8516FYLF
Package
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
48 Lead LQFP
ICS8516FYT
48 Lead LQFP on Tape and Reel
48 Lead "Lead-Free" LQFP
ICS8516FYLF
250 per tray
48 Lead "Lead-Free" LQFP
on Tape and Reel
ICS8516FYLFT
ICS8516FYLF
1000
0°C to 70°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8516FY
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REV. A JULY 30, 2004
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ICS8516
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-16
D
IFFERENTIAL
-
TO-LVDS CLOCK
D
ISTRIBUTION
CHIP
REVISION HISTORY SHEET
Description of Change
Rev
A
Table
T1
Page
Date
2
8
2
Pin Description table - added pins 47 thru 48.
3/31/03
5/6/03
Added LVDS Driver Termination in the Application Information section.
Pin Description Table - switched pin names for 45, 46 & 47,48
A
T1
T2
3
9
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Updated Differential Clock Input Interface section.
A
7/30/04
T8
12
Ordering Information Table - added Lead-Free part numbers.
8516FY
www.icst.com/products/hiperclocks.html
REV. A JULY 30, 2004
13
相关型号：
ICS8516FY-01
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
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ICS8516FY-01LFT
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
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ICS8516FY-01T
Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
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