ICS85210-21 [ICSI]
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER; 低歪曲率，双通道， 1到5差分至HSTL扇出缓冲器
| 型号： | ICS85210-21 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-HSTL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85210-21
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85210-21 is a low skew, high perfor- • Dual 1-to-5 HSTL bank outputs
ICS
mance dual 1-to-5 Differential-to-HSTL Fanout
• 2 selectable differential clock input pairs
HiPerClockS™
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLKx, nCLKx pairs can accept
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
most standard differential input levels.The ICS85210-21 is
characterized to operate from a 3.3V power supply.
Guaranteed output and part-to-part skew characteris-
tics make the ICS85210-21 ideal for those clock distri-
bution applications demanding well defined perfor-
mance and repeatability.
• Maximum output frequency: 650MHz
• Translates any single ended input signal to 3.3V
HSTL levels with resistor bias on nCLKx inputs
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
nQA0
CLK0
nCLK0
QA1
nQA1
QA2
nQA2
32 31 30 29 28 27 26 25
VDD
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QA3
QA3
nQA3
nQA3
QA4
CLK0
nCLK0
nc
QA4
nQA4
nQA4
QB0
ICS85210-21
CLK1
nCLK1
nQB0
QB1
QB0
nQB0
CLK1
nCLK1
nQB1
GND
QB1
nQB1
9
10 11 12 13 14 15 16
QB2
nQB2
QB3
nQB3
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
QB4
nQB4
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REV. A OCTOBER 6, 2003
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ICS85210-21
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1
Name
VDD
Type
Description
Power
Core supply pin.
No connect.
2, 5
nc
Unused
Input
3
CLK0
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
4
nCLK0
Input
6
CLK1
Input
7
nCLK1
Input
Pullup
Inverting differential clock input.
8
GND
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power supply ground.
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VDDO
Output supply pins.
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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ICS85210-21
Integrated
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OW
S
KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Input Power Supply Voltage
3.465
2.0
V
Output Power Supply Voltage
Power Supply Current
1.6
1.8
V
120
mA
mA
IDDO
Output Supply Current
No Load
0
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
DD = VIN = 3.465V
5
µA
µA
µA
µA
V
IIH
Input High Current
VDD = VIN = 3.465V
150
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLKx and nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1
1.4
V
Output Low Voltage;
NOTE 1
VOL
0
40ꢀ x (VOH - VOL) + VOL
0.6
0.4
60ꢀ x (VOH - VOL) + VOL
1.1
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
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KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
650
2
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 650MHz
1.5
tsk(o)
tsk(pp)
tR/tF
50
ps
350
700
53
ps
30ꢀ to 70ꢀ @ 50MHz
300
47
ps
odc
Output Duty Cycle
ꢀ
All parameters measured at 400MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS85210-21
Integrated
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Systems, Inc.
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OW
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KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
VDD
VDD
SCOPE
Qx
nCLK0,
nCLK1
HSTL
VPP
VCMR
Cross Points
CLK0,
CLK1
nQx
GND
GND
0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
Qx
PART 1
nQx
Qy
nQy
PART 2
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK0,
nCLK1
70ꢀ
tF
70ꢀ
CLK0,
CLK1
VSWING
30ꢀ
Clock
30ꢀ
nQAx,
nQBx
QAx,
Outputs
tR
QBx
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQAx,
nQBx
QAx,
QBx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS85210-21
Integrated
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KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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D
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-
TO-HSTL FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS HSTL drivers. If you are using an HSTL driver from
the most common driver types.The input interfaces suggested another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS HSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85210-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85210-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 416mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 32.8mW = 328mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 328mW = 744mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.744W * 42.1°C/W = 101°C. This is well below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 3. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DDO_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DDO_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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Systems, Inc.
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OW
S
KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85210-21 is: 1216
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KEW, DUAL, 1-TO-5
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS85210AY-21
Marking
Package
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to70°C
ICS85210AY-21
ICS85210AY-21
32 lead LQFP
ICS85210AY-21T
32 lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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-
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BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
Throughout data sheet changed LVHSTL to HSTL.
2
2
6
7
Pin Description Table changed VDD description from Positive to Core.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Revised Single Ended Signal Driving Differential Input diagram.
Added Differential Clock Input Interface section.
1
2
A
10/6/03
Updated data sheet format.
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