ICS8523AI03L [ICSI]
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER; 低偏移， 1到4差分至LVHSTL扇出缓冲器
| 型号： | ICS8523AI03L |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8523I-03 is a low skew, high perfor- • 4 differential LVHSTL compatible outputs
ICS
mance 1-to-4 Differential-to-LVHSTL fanout buffer
• Selectable differential CLK0, nCLK0 and CLK1, nCLK1
clock inputs
HiPerClockS™
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523I-03 has two selectable clock inputs.
• Clock input pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
The input pairs can accept most standard differential input
levels. The clock enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to LVHSTL
levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8523I-03 ideal for those applications demand-
ing well defined performance and repeatability.
• Output skew: 50ps (maximum)
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.2ns (typical)
• VOH = 1V (maximum)
• 3.3V core, 1.8V output operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
D
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
CLK_EN
Q0
GND
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
nc
Q
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
LE
CLK0
0
nCLK0
CLK1
Q0
nQ0
1
nCLK1
Q1
nQ1
9
10
nc
VDD
CLK_SEL
nQ3
Q2
nQ2
ICS8523I-03
20-LeadTSSOP
Q3
nQ3
6.5mm x 4.4mm x 0.92mm body package
G Package
TopView
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
1
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Power supply ground.
1
GND
Power
Input
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
2
3
CLK_EN
Pullup
Clock select input. When HIGH, selects differential CLK1, nCLK1
CLK_SEL
Input
Pulldown inputs. When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levels.
4
CLK0
nCLK0
CLK1
Input
Input
Pulldown Non-inverting differential clock input.
5
Pullup
Inverting differential clock input.
6
Input
Pulldown Non-inverting differential clock input.
7
nCLK1
nc
Input
Pullup
Inverting differential clock input.
No connect.
8, 9
10
Unused
Power
Output
Power
Output
Output
Output
VDD
Core supply pin.
11, 12
13, 18
14, 15
16, 17
19, 20
nQ3, Q3
VDDO
Differential output pair. LVHSTL interface levels.
Output supply pins.
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
2
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ3
0
0
1
1
0
1
0
1
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 , nCLK0 and CLK1, nCLK1 inputs as described
in Table 3B.
Enabled
Disabled
nCLK0, nCLK1
CLK0, CLK1
CLK_EN
nQ0:nQ3
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK0 or CLK1 nCLK0 or nCLK1
Q0:Q3
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ3
HIGH
LOW
0
0
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
3
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
73.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.465
2.0
V
V
Output Power Supply Voltage
Power Supply Current
1.6
1.8
55
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage CLK_EN, CLK_SEL
2
VDD + 0.3
V
Input Low Voltage CLK_EN, CLK_SEL
-0.3
0.8
5
V
CLK_EN
Input High Current
CLK_SEL
V
DD = VIN = 3.465V
µA
µA
µA
µA
IIH
VDD = VIN = 3.465V
150
CLK_EN
Input Low Current
CLK_SEL
VDD = 3.465V, VIN = 0V
-150
-5
IIL
V
DD = 3.465V, VIN = 0V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
V
DD = VIN = 3.465V
DD = VIN = 3.465V
5
µA
µA
µA
µA
V
IIH
Input High Current
V
150
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
4
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
0.7
0
1.0
0.4
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
0.4
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Maximum Output Frequency
650
1.5
50
MHz
ns
ps
ps
ps
ꢀ
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
IJ 650MHz
0.9
1.2
tsk(o)
tsk(pp)
tR / tF
400
500
55
20ꢀ to 80ꢀ
ƒ> 200MHz
IJ 200MHz
150
45
50
odc
Output Duty Cycle
48
52
ꢀ
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
5
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V 5ꢀ
1.8V 0.2V
VDD
SCOPE
VDD
Qx
VDDO
nCLK0,
nCLK1
VPP
VCMR
Cross Points
LVHSTL
CLK0,
CLK1
nQx
GND
GND = 0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0,
nCLK1
80ꢀ
tF
80ꢀ
CLK0,
CLK1
VOD
Clock
20ꢀ
20ꢀ
nQ0:nQ3
Outputs
tR
Q0:Q3
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ3
Q0:Q3
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
6
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
7
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
8
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using the input is driven by an LVHSTL driver. CLK_EN is set at logic
ICS8523I-03 LVHSTL buffer. Figure 3 shows a schematic ex- low to select CLK0/nCLK0 input.
ample of the ICS8523I-03 LVHSTL Clock buffer.In this example,
Zo = 50
+
Zo = 50
-
3.3V
R2
50
R1
50
R12
1K
U1
1.8V
Zo = 50
Zo = 50
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GND
Q0
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
+
-
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
NC
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
1.8V
R4
50
R3
50
R11
1K
NC
VDD
3.3V
10
nQ3
LVHSTL Driver
R9
50
R10
50
C1
0.1u
ICS8523-03
Zo = 50
+
-
1.8V
Zo = 50
C2
0.1u
C3
0.1u
R6
50
R5
50
Zo = 50
Zo = 50
+
-
R8
50
R7
50
FIGURE 4. EXAMPLE ICS8523I-03 LVHSTL CLOCK OUTPUT BUFFER SCHEMATIC
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
9
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523I-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523I-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32.8mW = 131mW
Total Power_MAX (3.465V, with all outputs switching) = 190mW + 131mW = 321mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.321W * 66.6°C/W = 106.4°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
10
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 5. LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MAX
OH_MAX
L
DDO_MAX
/R ) * (V
- V
)
OL_MAX
L
DDO_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
11
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8523I-03 is: 472
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
12
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
13
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8523AGI-03
Marking
Package
Count
72 per tube -40°C to 85°C
2500 -40°C to 85°C
72 per tube -40°C to 85°C
2500 -40°C to 85°C
Temperature
ICS8523AGI03
ICS8523AGI03
ICS8523AI03L
20 lead TSSOP
ICS8523AGI-03T
ICS8523AGI-03LN
20 lead TSSOP on Tape and Reel
20 lead "Lead-Free" TSSOP
20 lead "Lead-Free" TSSOP on
Tape and Reel
ICS8523AGI-03LNT
ICS8523AI03L
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional
processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
14
ICS8523I-03
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-4
D
IFFERENTIAL
-
TO-LVHSTL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
1
8
Features section - added Lead-Free bullet.
Updated Differential Clock Input Interface section and deleted
LVPECL Clock Input Interface section.
A
9/13/04
T9
T9
14
14
Added Lead-Free marking to Ordering Information table.
Ordering Information Table - corrected Lead-Free Part Number from
"LF" to "LN".
A
10/5/04
8523AGI-03
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 5, 2004
15
相关型号：
ICS8523BGI-T
LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20
IDT
ICS8523BGLFT
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MS-153, TSSOP-20
IDT
©2020 ICPDF网 联系我们和版权申明