ICS8523BGT [ICSI]
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER; 低偏移， 1到4差分至LVHSTL扇出缓冲器
| 型号： | ICS8523BGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8523 is a low skew, high perfor- • 4 differential 1.8V LVHSTLoutputs
mance 1-to-4 Differential-to-LVHSTL fanout buffer
and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8523 has two selectable clock inputs. The
• Selectable CLK, nCLK or LVPECL clock inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTLinput levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 1.8V LVHSTL
levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8523 ideal for those applications demanding
well defined performance and repeatability.
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.6ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
20
19
18
17
16
15
14
13
12
11
1
2
Q0
D
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
CLK_EN
nQ0
VDDO
Q1
nQ1
Q2
nQ2
VDDO
Q3
Q
3
4
5
6
7
8
LE
CLK
nCLK
PCLK
0
1
Q0
nQ0
nPCLK
Q1
nQ1
9
10
nc
VDD
CLK_SEL
nQ3
Q2
nQ2
ICS8523
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
8523BG
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REV. B JULY 31, 2001
1
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GND
Power
Input
Power supply ground. Connect to ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVCMOS / LVTTL interface levels.
2
3
CLK_EN
Pullup
Clock select input. When HIGH, selects differential PCLK, nPCLK
CLK_SEL
Input
Pulldown inputs. When LOW, selects CLK, nCLK inputs.
LVCMOS / LVTTL interface levels.
4
CLK
nCLK
Input
Input
Pulldown Non-inverting differential clock input.
5
Pullup
Inverting differential clock input.
6
PCLK
nPCLK
nc
Input
Pulldown Non-inverting differential LVPECL clock input.
7
Input
Pullup
Inverting differential LVPECL clock input.
No connect.
8, 9
10
Unused
Power
Output
Power
Output
Output
Output
VDD
Positive supply pin. Connect to 3.3V.
Differential output pair. LVHSTL interface levels.
Output supply pins. Connect to 1.8V.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
11, 12
13, 18
14, 15
16, 17
19, 20
nQ3, Q3
VDDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK, nCLK
Input Capacitance PCLK, nPCLK
CLK_EN, CLK_SEL
4
4
4
pF
pF
CIN
pF
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN
Input Pulldown Resistor
8523BG
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REV. B JULY 31, 2001
2
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0 thru Q3
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ3
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ3
Q0 - Q3
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
Q0 thru Q3
LOW
nQ0 thru nQ3
HIGH
0
0
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
HIGH
LOW
0
Biased; NOTE 1
LOW
HIGH
1
Biased; NOTE 1
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential
input to accept single ended levels.
8523BG
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REV. B JULY 31, 2001
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ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
73.2°C/W
Storage Temperature, TSTG
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Input Power Supply Voltage
3.465
2.0
V
V
Output Power Supply Voltage
Power Supply Current
1.6
1.8
50
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage CLK_EN, CLK_SEL
2
3.765
0.8
V
Input Low Voltage CLK_EN, CLK_SEL
-0.3
V
CLK_EN
Input High Current
CLK_SEL
V
DD = VIN = 3.465V
5
µA
µA
µA
µA
IIH
VDD = VIN = 3.465V
150
CLK_EN
Input Low Current
CLK_SEL
VDD = 3.465V, VIN = 0V
-150
-5
IIL
V
DD = 3.465V, VIN = 0V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
nCLK
CLK
V
DD = VIN = 3.465V
DD = VIN = 3.465V
5
µA
µA
µA
µA
V
IIH
Input High Current
V
150
nCLK
CLK
V
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
V
DD - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
8523BG
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REV. B JULY 31, 2001
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ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
PCLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nPCLK
PCLK
V
-5
-150
0.3
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
1
VCMR
Common Mode Input Voltage; NOTE 1, 2
1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1
1.4
V
Output Low Voltage;
NOTE 1
VOL
0
40% x (VOH - VOL) + VOL
0.75
0.4
60% x (VOH - VOL) + VOL
1.25
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum Units
650
1.6
30
MHz
ns
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 650MHz
1.3
tsk(o)
tsk(pp)
tR
ps
150
700
700
55
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
45
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 500MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8523BG
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REV. B JULY 31, 2001
5
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VDDO
VDD
SCOPE
Qx
LVHSTL
VDD = 3.3V ± 5%
VDDO = 1.8V ± 0.2V
nQx
GND = 0V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VDD
CLK, PCLK
VPP
VCMR
Cross Points
nCLK, nPCLK
GND
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
8523BG
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REV. B JULY 31, 2001
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ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
Qx
PART 1
nQx
Qy
PART 2
nQy
tsk(pp)
FIGURE 5 - PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
CLK, PCLK
nCLK, nPCLK
Q0 - Q3
nQ0 - nQ3
tPD
FIGURE 7 - PROPAGATION DELAY
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 8 - odc & tPERIOD
8523BG
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REV. B JULY 31, 2001
7
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8523BG
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REV. B JULY 31, 2001
8
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8523.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW
Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 32mW = 128mW
Total Power_MAX (3ꢀ465V, with all outputs switching) = 173ꢀ3mW + 128mW = 301ꢀ3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.301W * 66.6°C/W = 90.05°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8523BG
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REV. B JULY 31, 2001
9
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 10.
VDD
Q1
VOUT
RL
Ω
50
FIGURE 10 - LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
DD
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MAX
OH_MAX
L
DD_MAX
/R ) * (V
- V
)
OL_MAX
L
DD_MAX
OL_MAX
•
•
For logic high, V = V
= V
– 1.2V
OUT
OH_MAX
DD_MAX
For logic low, V = V
= V
– 0.4V
OUT
OL_MAX
DD_MAX
Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L= 32mW
8523BG
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REV. B JULY 31, 2001
10
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8523 is: 472
8523BG
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REV. B JULY 31, 2001
11
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
20
MAX
N
A
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
8523BG
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REV. B JULY 31, 2001
12
ICS8523
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8523BG
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to70°C
ICS8523BG
ICS8523BG
20 lead TSSOP
ICS8523BGT
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
8523BG
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REV. B JULY 31, 2001
13
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