ICS8524AY [ICSI]
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER; 低偏移， 1到22差分至HSTL扇出缓冲器
| 型号： | ICS8524AY |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER |
| 文件： | 总17页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8524 is a low skew, 1-to-22 Differential- • 22 differential HSTL outputs
ICS
to-HSTL Fanout Buffer and a member of the
HiPerClockS™Family of High Performance Clock
Solutions from ICS.The ICS8524 has two select-
able clock inputs.The CLK, nCLK pair can accept
each with the ability to drive 50Ω to ground
HiPerClockS™
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
most standard differential input levels.The PCLK, nPCLK pair
can accept LVPECL, CML, or SSTL input levels.The device is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the OE pin.The
ICS8524’s low output and part-to-part skew characteristics
make it ideal for workstation, server, and other high performance
clock distribution applications.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 500MHz
• Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to HSTL levels with resistor bias on nCLK input
• Output skew: 80ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Jitter, RMS: 0.04ps (typical)
• LVPECL and HSTL mode operating voltage supply range:VDD
= 3.3V 5ꢀ, VDDO = 1.6V to 2V, GND = 0V
• 0°C to 85°C ambient operating temperature
• Pin compatible with the SY89824L and NB100EP223
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDDO
Q14
VDDO
nQ6
Q6
0
1
nCLK
22
22
nQ14
Q15
Q0:Q21
nQ0:nQ21
nQ5
Q5
PCLK
nPCLK
nQ15
Q16
nQ4
Q4
LE
D
nQ16
Q17
Q
nQ3
Q3
ICS8524
OE
nQ17
Q18
nQ2
Q2
nQ18
Q19
nQ1
Q1
nQ19
Q20
nQ0
Q0
nQ20
VDDO
VDDO
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 16
64-LeadTQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
TopView
8524AY
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REV. B SEPTEMBER 18, 2003
1
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 16, 17, 32,
33, 48, 49, 64
VDDO
Power
Output supply pins.
2, 3, 12, 13
nc
VDD
CLK
Unused
Power
Input
No connect.
4
5
Core supply pin.
Pulldown Non-inverting differential clock input pair.
Pullup/
Pulldown
6
nCLK
Input
Inverting differential clock input pair. Biased to 2/3 VCC.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs.
7
CLK_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
8
PCLK
nPCLK
GND
OE
Input
Input
Power
Input
Pulldown Non-inverting differential LVPECL clock input pair.
Pullup/
9
Inverting differential LVPECL clock input pair. Biased to 2/3 VCC.
Power supply ground.
Pulldown
Pullup
10
11
Output enable. Controls enabling and disabling of outputs
Q0:Q21, nQ0:nQ21. LVCMOS / LVTTL interface levels.
14, 15
18, 19
20, 21
22, 23
24, 25
26, 27
28, 29
30, 31
34, 35
36, 37
38, 39
40, 41
42, 43
44, 45
46, 47
50, 51
52, 53
54, 55
56, 57
58, 59
60, 61
62, 63
nQ21, Q21
nQ20, Q20
nQ19, Q19
nQ18, Q18
nQ17, Q17
nQ16, Q16
nQ15, Q15
nQ14, Q14
nQ13, Q13
nQ12, Q12
nQ11, Q11
nQ10, Q10
nQ9, Q9
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
Differential clock outputs. HSTL interface levels.
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8524AY
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REV. B SEPTEMBER 18, 2003
2
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
37
75
RPULLDOWN Input Pulldown Resistor
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nQ0:nQ21
HIGH
OE
0
CLK_SEL
Q0:Q21
LOW
0
1
0
1
0
LOW
HIGH
1
CLK
nCLK
1
PCLK
nPCLK
nCLK,
nPCLK
Enabled
Disabled
CLK,PCLK
OE
nQ0 :nQ21
Q0 :Q21
FIGURE 1. OE TIMING DIAGRAM
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REV. B SEPTEMBER 18, 2003
3
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
22.3°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA=0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
1.6
3.3
1.8
3.465
2.0
V
Ouptut Power Supply Voltage
Positive Supply Current
Output Supply Current
V
220
mA
mA
IDDO
No Load
1
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA=0°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE, CLK_SEL
Input Low Current OE, CLK_SEL
µA
µA
IIL
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA=0°C TO 85°C
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
Minimum Typical Maximum Units
IIH
Input High Current CLK, nCLK
150
µA
µA
V
IIL
Input Low Current CLK, nCLK
Peak-to-Peak Input Voltage
-150
0.15
VPP
VCMR
1.3
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
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REV. B SEPTEMBER 18, 2003
4
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA=0°C TO 85°C
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
Minimum Typical Maximum Units
IIH
Input High Current PCLK, nPCLK
150
µA
µA
V
IIL
Input Low Current PCLK, nPCLK
Peak-to-Peak Input Voltage
-150
0.3
VPP
VCMR
1
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4E. HSTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA=0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.4
0.4
60
V
V
VOL
Output Low Voltage; NOTE 1
VOX
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
0.6
ꢀ
V
VSWING
1.1
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V 0.2V, TA=0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
fMAX
Output Frequency
500
2.7
80
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
1.7
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
700
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.04
ps
tR / tF
tS
Output Rise/Fall Time
Setup Time
20ꢀ to 80ꢀ
300
1.0
0.5
49
700
ps
ns
ns
ꢀ
tH
Hold Time
IJ 133MHz
51
52
odc
Output Duty Cycle
133 < IJ 266MHz
48
ꢀ
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions at the same temperature. Using the same type of inputs on each device,
the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8524AY
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REV. B SEPTEMBER 18, 2003
5
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Input/Output Additive
Phase Jitter at 156.25MHz
= 0.04ps (typical)
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
140
-
-150
160
-
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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REV. B SEPTEMBER 18, 2003
6
ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.8V 0.2V
3.3V 5ꢀ
VDD
SCOPE
VDD
Qx
VDDO
nCLK, nPCLK
VPP
VCMR
Cross Points
HSTL
CLK, PCLK
GND
nQx
GND
0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
nQy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK, nPCLK
CLK, PCLK
nQ0:nQ21
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
Q0:Q21
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ21
Q0:Q21
VOX
60ꢀ
50ꢀ
40ꢀ
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT CROSSOVER VOLTAGE
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8524AY
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS HSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS HSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 4A to 4E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
CLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
S
CHEMATIC
E
XAMPLE
Figure 5 shows a schematic example of the ICS8524. In this power pin. For ICS8524, the unused clock outputs can be left
example, the input is driven by an ICS HiPerClockS HSTL driver. floating.
The decoupling capacitors should be physically located near the
Zo = 50
+
Zo = 50
-
VDDO=1.8V
U3
R2
50
R1
50
1.8V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDO
nc
VDDO
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Q12
nQ12
Q13
nQ13
VDDO
nc
VDD=3.3V
Zo = 50 Ohm
Zo = 50 Ohm
VDD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
OE
nc
nc
nQ21
Q21
VDDO
C9
0.1u
R12 1K
LVHSTL Driver
R9
50
R10
50
VDD=3.3V
R11 1K
ICS8524
Zo = 50
+
-
Zo = 50
(U1-1)VDDO=1.8V(U1-16)
(U1-17) (U1-32) (U1-33) (U1-48) (U1-49) (U1-64)
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
R8
50
R7
50
FIGURE 5. ICS8524 HSTL BUFFER SCHEMATIC EXAMPLE
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to solder as shown in Figure 6.For further information, please re-
the P.C. board.The expose metal pad is ground pad connected fer to the Application Note on Surface Mount Assembly of
to ground plane through thermal via. The exposed pad on the Amkor’sThermally /Electrically Enhance Leadframe Base Pack-
device to the exposed metal pad on the PCB is contacted through age, Amkor Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
F
IGURE 6. P.C. BOARD FOR
EXPOSED
PAD
T
HERMAL
R
ELEASE
PATH
EXAMPLE
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8524.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8524 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 220mA = 762.3mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 22 * 32.8mW = 721.6mW
Total Power_MAX (3.465V, with all outputs switching) = 762.3mW + 721.6mW = 1483.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming an
air flow of 500 linear feet per minute and a multi-layer board, the appropriate value is 15.1°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.484W * 15.1°C/W = 107.4°C.This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 64-PIN TQFP, E-PAD FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3°C/W
17.2°C/W
15.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8524AY
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
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L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 7.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 7. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DDO_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DDO_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
8524AY
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3°C/W
17.2°C/W
15.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8524 is: 1474
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TQFP, E-PAD
EXPOSED PAD
D2
E2
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCD
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
64
--
--
1.20
0.15
1.05
0.27
0.20
A1
A2
b
0.05
.95
--
1.0
0.17
0.09
0.22
c
--
D
12.00 BASIC
10.00 BASIC
5.00 Ref.
12.00 BASIC
10.00 BASIC
5.00 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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REV. B SEPTEMBER 18, 2003
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ICS8524
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-22
D
IFFERENTIAL
-
TO-HSTL FANOUT
BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
160 per tray
500
Temperature
0°C to 85°C
0°C to 85°C
ICS8524AY
ICS8524AY
ICS8524AY
64 lead TQFP, E-Pad
ICS8524AYT
64 lead TQFP, E-Pad on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. B SEPTEMBER 18, 2003
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ICS8524
LOW SKEW, 1-TO-22
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
T5
Page
Date
1
5
6
Added Phase Jitter to Features section.
B
AC Characteristics Table - added Phase Jitter row.
Added Additive Phase Jitter section.
9/18/03
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REV. B SEPTEMBER 18, 2003
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