ICS8525BG [ICSI]

LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER; 低偏移， 1到4 LVCMOS - TO- LVHSTL扇出缓冲器


型号：	ICS8525BG
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	LOW SKEW, 1-TO-4 LVCMOS-TO-LVHSTL FANOUT BUFFER 低偏移， 1到4 LVCMOS - TO- LVHSTL扇出缓冲器
文件：	总12页 (文件大小：115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

GENERAL DESCRIPTION

FEATURES

The ICS8525 is a low skew, high performance • 4 differential 1.8V LVHSTL outputs

1-to-4 LVCMOS-to-LVHSTL fanout buffer and a

• Selectable LVCMOS / LVTTL clock inputs for redundant

and multiple frequency fanout applications

HiPerClockS™

member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The

ICS8525 has two selectable clock inputs that ac-

• Maximum output frequency up to 266MHz

cept LVCMOS or LVTTL input levels and translate them to

1.8V LVHSTL levels. The clock enable is internally synchro-

nized to eliminate runt pulses on the outputs during asyn-

chronous assertion/deassertion of the clock enable pin.

• Translates LVCMOS and LVTTL levels to 1.8V

LVHSTL levels

• Output skew: 35ps (maximum)

Guaranteed output and part-to-part skew characteristics

make the ICS8525 ideal for those applications demanding

well defined performance and repeatability.

• Part-to-part skew: 150ps (maximum)

• Propagation delay: 1.9ns (maximum)

• 3.3V core, 1.8V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

GND

CLK_EN

CLK_SEL

CLK0

CLK_EN

nQ0

V^DDO

nQ1

nQ2

V^DDO

CLK0

CLK1

nQ0

CLK1

nQ1

V^DD

CLK_SEL

nQ3

nQ2

ICS8525

nQ3

20-Lead TSSOP

6.5mm x 4.4mm x 0.92mm Package Body

G Package

Top View

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

GND

Power

Input

Power supply ground. Connect to ground.

Synchronizing clock enable. When HIGH, clock outputs follow clock

input. When LOW, Q outputs are forced low, nQ outputs are forced high.

LVCMOS / LVTTL interface levels.

Clock select input. When HIGH, selects CLK1 input.

When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.

CLK_EN

Pullup

Pulldown

CLK_SEL

Input

CLK0

CLK1

Input

Pulldown LVCMOS / LVTTL clock input.

No connect.

5, 7, 8, 9

Unused

Power

Output

V_DD

Positive supply pin. Connect to 3.3V.

Output supply pins. Conncect to 1.8V.

Differential output pair. LVHSTL interface levels.

13, 18

11, 12

14, 15

16, 17

19, 20

V_DDO

nQ3, Q3

nQ2, Q2

nQ1, Q1

nQ0, Q0

NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

Parameter

Test Conditions

Minimum Typical Maximum Units

CLK0, CLK1

C_IN

Input Capacitance

CLK_EN,

CLK_SEL

R_PULLUP

Input Pullup Resistor

KΩ

R_PULLDOWN

Input Pulldown Resistor

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

CLK_EN

CLK_SEL

Selected Source

CLK0

Q0 thru Q3

Disabled; LOW

Enabled

nQ0 thru nQ3

Disabled; HIGH

Enabled

CLK1

CLK0

CLK1

Enabled

After CLK_EN switches, the clock ooutputs are disabled or enabled following a rising and falling input clock edge

as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.

Disabled

Enabled

CLK0, CLK1

CLK_EN

nQ0 - nQ3

Q0 - Q3

FIGURE 1 - CLK_EN TIMING DIAGRAM

TABLE 3B. CLOCK INPUT FUNCTION TABLE

Inputs

Outputs

CLK0 or CLK1

Q0 thru Q3

LOW

nQ0 thru nQ3

HIGH

LOW

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V_DDx

Inputs, V_I

4.6V

-0.5V to V_DD+ 0.5V

-0.5V to V_DDO+ 0.5V

Outputs, V_O

Package Thermal Impedance, θ_JA

Storage Temperature, T_STG

73.2°C/W (0lfpm)

-65°C to 150°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These rat-

ings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those

listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= 3.3V±5%, V_DDO= 1.8V±0.2V, TA = 0°C TO 70°C

Symbol

V_DD

Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum Units

Positive Supply Voltage

Output Supply Voltage

Power Supply Current

3.465

2.0

V_DDO

I_DD

1.6

1.8

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V_DD= 3.3V±5%, V_DDO= 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

CLK0, CLK1

3.765

1.3

V_IH

V_IL

I_IH

Input High Voltage

CLK_EN,

CLK_SEL

CLK0, CLK1

-0.3

Input Low Voltage

Input High Current

Input Low Current

CLK_EN,

0.8

CLK_SEL

CLK0, CLK1,

CLK_SEL

V_DD= V_IN= 3.465V

150

µA

CLK_EN

_DD= V_IN= 3.465V

_DD= 3.465V, V_IN= 0V

V_DD= 3.465V, V_IN= 0V

CLK0, CLK1,

CLK_SEL

-5

I_IL

CLK_EN

-150

TABLE 4C. LVHSTL DC CHARACTERISTICS, V_DD= 3.3V±5%, V_DDO= 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output High Voltage;

NOTE 1

Output Low Voltage;

NOTE 1

V_OH

V_OL

1.2

0.4

40% x (V_OH-V_OL) + V_OL

0.75

V_OX

Output Crossover Voltage

60% x (V_OH-V_OL) + V_OL

1.25

Peak-to-Peak

Output Voltage Swing

V_SWING

NOTE 1: Outputs terminated with 50Ω to GND.

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

TABLE 5. AC CHARACTERISTICS, V_DD= 3.3V±5%, V_DDO= 1.8V±0.2V, TA = 0°C TO 70°C

Symbol Parameter

f_MAXMaximum Output Frequency

t_PD

Test Conditions

Minimum Typical

Maximum

266

Units

MHz

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 4

Part-to-Part Skew; NOTE 3, 4

Output Rise Time

ƒ≤ 266MHz

1.0

1.9

tsk(o)

tsk(pp)

t_R

150

20% to 80% @ 50MHz

300

700

t_F

Output Fall Time

700

odc

Output Duty Cycle

All parameters measured at 266MHz unless noted otherwise.

The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.

NOTE 1: Measured from the 50% point of the input to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

PARAMETER MEASUREMENT INFORMATION

V_DDO

V_DD

SCOPE

LVHSTL

V_{DD =}3.3V ± 5%

V_{DDO =}1.8V ± 0.2V

nQx

GND = 0V

FIGURE 2 - OUTPUT LOAD TEST CIRCUIT

nQx

nQy

tsk(o)

FIGURE 3 - OUTPUT SKEW

PART1

nQx

PART2

nQy

tsk(pp)

FIGURE 4 - PART-TO-PART SKEW

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

80%

V_SWING

20%

Clock Inputs

and Outputs

t_R

t_F

FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME

CLK0, CLK1

Q0 - Q3

nQ0 - nQ3

t_PD

FIGURE 6 - PROPAGATION DELAY

CLK0, CLK 1, Qx

nQx

Pulse Width

t_PERIOD

t_PW

odc =

t_PERIOD

FIGURE 7 - odc & t_PERIOD

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS8525.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8525 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_DD= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{DD_MAX}* I_{DD_MAX}= 3.465V * 50mA = 173.25mW

Power (outputs)_MAX= 32mW/Loaded Output pair

If all outputs are loaded, the total power is 4 x 32mW = 128mW

Total Power_{_MAX}(3.465V, with all outputs switching) = 173.25mW + 128mW = 301.25mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of

the device. The maximum recommended junction temperature for HiPerClockS^TMdevices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

θ_JA= junction-to-ambient thermal resistance

Pd_total = Total device power dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming a

moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.301W * 66.6°C/W = 90.05°C. This is well below the limit of 125°C

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

Table 6. Thermal Resistance _JAfor 20-pin TSSOP, Forced Convection

_JAby Velocity (Linear Feet per Minute)

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

73.2°C/W

98.0°C/W

66.6°C/W

88.0°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVHSTL output driver circuit and termination are shown in Figure 8.

V_DDO

V_OUT

R L

V_DDO- 2V

FIGURE 8 - LVHSTL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a

termination voltage of V - 2V.

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = (V

Pd_L = (V

/R ) * (V

- V

)

OH_MAX

DD_MAX

/R ) * (V

- V

)

OL_MAX

DD_MAX

OL_MAX

•

For logic high, V = V

= V

– 1.2V

OUT

OH_MAX

DD_MAX

For logic low, V = V

= V

– 0.4V

OUT

OL_MAX

DD_MAX

Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW

Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

RELIABILITY INFORMATION

TABLE 7. θ_JA^VS. AIR FLOW TABLE

_JAby Velocity (Linear Feet per Minute)

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

114.5°C/W

73.2°C/W

98.0°C/W

66.6°C/W

88.0°C/W

63.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS8525 is: 484

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

PACKAGE OUTLINE - G SUFFIX

TABLE 8. PACKAGE DIMENSIONS

Millimeters

MAX

SYMBOL

MIN

1.20

0.05

0.80

0.19

0.09

6.40

0.15

1.05

0.30

0.20

6.60

6.40 BASIC

4.50

4.30

0.65 BASIC

0.75

0.45

0°

8°

aaa

0.10

REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525

LOW SKEW, 1-TO-4

LVCMOS-TO-LVHSTL FANOUT BUFFER

Integrated

Circuit

Systems, Incꢀ

TABLE 9. ORDERING INFORMATION

Part/Order Number

Marking

Package

Count

72 per tube

2500

Temperature

0°C to 70°C

ICS8525BG

20 lead TSSOP

ICS8525BG-T

20 lead TSSOP on Tape and Reel

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or

for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-

mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use

in life support devices or critical medical instruments.

8525BG

www.icst.com/products/hiperclocks.html

REV. B JULY 27, 2001

ICS8525BG [ICSI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E