ICS8530-01 [ICSI]
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER; 低偏移, 1至16差分至3.3V的LVPECL扇出缓冲器型号: | ICS8530-01 |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
文件: | 总12页 (文件大小:127K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8530-01 is a low skew, 1-to-16 Differen- • 16 differential 3.3V LVPECL outputs
tial-to-3.3V LVPECL Fanout Buffer and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The CLK, nCLK
pair can accept most standard differential input
• CLK, nCLK input pair
HiPerClockS™
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
levels. The high gain differential amplifier accepts peak-to-
peak input voltages as small as 150mV as long as the com-
mon mode voltage is within the specified minimum and maxi-
mum range.
• Maximum output frequency up to 500MHz
• Translates any single-ended input signal to 3.3V LVPECL
levels with a resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8530-01 ideal for those clock distribution appli-
cations demanding well defined performance and repeatabil-
ity.
• Output skew: 75ps (maximum)
• Part-to-part skew: 250ps (maximum)
• 3.3V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
48 47 46 45 44 43 42 41 40 39 38 37
Q0
Q15
CLK
VCCO
nQ0
Q0
VCCO
Q11
nQ11
Q10
nQ10
VEE
1
36
35
34
33
32
31
30
29
28
27
26
25
nQ0
nQ15
2
Q1
nQ1
Q14
nQ14
3
4
nQ1
Q1
5
Q2
nQ2
Q13
nQ13
6
ICS8530-01
VEE
Q9
7
Q3
nQ3
Q12
nQ12
nQ2
Q2
nQ9
Q8
8
9
Q4
nQ4
Q11
nQ11
nQ3
Q3
nQ8
VCCO
VCC
10
11
12
Q5
nQ5
Q10
nQ10
Vcco
13 14 15 16 17 18 19 20 21 22 23 24
Q6
nQ6
Q9
nQ9
Q7
nQ7
Q8
nQ8
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8530DY-01
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REV. B AUGUST 8, 2001
1
ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 14, 24,
25, 35, 38, 48
VCCO
Power
Output supply pins. Connect to 3.3V.
2, 3
4, 5
Q11, nQ11
Q10, nQ10
VEE
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins. Connect to ground.
6, 19, 30, 43
7, 8
Q9, nQ9
Q8, nQ8
VCC
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Positive supply pins. Connect to 3.3V.
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
36
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
CLK
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels..
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Non-inverting differential clock input.
37
nCLK
Input
Pullup
Inverting differential clock input.
39, 40
41, 42
44, 45
46, 47
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK, nCLK
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
Input Pulldown Resistor
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0 thru Q15
LOW
nQ0 thru nQ15
HIGH
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
LOW
HIGH
1
Biased; NOTE 1
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section on page 7, Figure 8, which discusses wiring the differential
input to accept single ended levels.
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCCO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
47.9°C/W
Storage Temperature, TSTG
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Input/core Supply Voltage
3.465
3.465
120
V
V
Output Supply Voltage
Power Supply Current
3.135
3.3
mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
Minimum Typical
Maximum Units
CLK
150
5
µA
µA
µA
µA
V
nCLK
CLK
-5
IIL
Input Low Current
nCLK
VCC = 3.465V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
V
EE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 1.0
VCCO - 1.7
0.85
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO-2V.
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
500
2
MHz
ns
tPD
IJ 500MHz
1
tsk(o)
tsk(pp)
tR
75
ps
88
50
250
700
700
53
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
47
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
%
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B AUGUST 8, 2001
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCCO
VCC
SCOPE
Qx
LVPECL
VCC = 2V ± 5%
VCCO = 2V ± 5%
nQx
VEE = -1.3V ± 0.135V
FIGURE 1 - OUTPUT LOAD TEST CIRCUIT
VCC
CLK
VPP
VCMR
Cross Points
nCLK
VEE
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 3 - OUTPUT SKEW
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REV. B AUGUST 8, 2001
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Qx
PART1
nQx
Qy
PART2
nQy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
CLK
nCLK
Q0 - Q15
nQ0 - nQ15
tPD
FIGURE 6 - PROPAGATION DELAY
CLK, Qx
nCLK, nQx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
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REV. B AUGUST 8, 2001
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. B AUGUST 8, 2001
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8530-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8530-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA= 415.8mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 16 * 30.2mW = 483.2mW
Total Power_MAX (3.465V, with all outputs switching) = 415.8mW + 483.2mW = 899mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.899W * 47.9°C/W = 113.1°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 9.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 9 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
– (V
- 2V))/R ]*(V
- V
)
OH_MAX
OH_MAX
CC_MAX
L
CC_MAX
– (V
- 2V))/R ]*(V
- V
)
OL_MAX
CC_MAX
L
CC_MAX
OL_MAX
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
Using V
= 2.625, this results in V
= 1.625V
= 0.925V
CC_MAX
OH_MAX
For logic low, V = V
= V – 1.7V
CC_MAX
OUT
OL_MAX
Using V
= 2.625, this results in V
OL_MAX
CC_MAX
Pd_H = [(1.625V - (2.625V - 2V))/50 Ω]*(1V) = 20mW
Pd_L = [(0.925V - (2.625V - 2V))/50 Ω]*(1.7) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
200
0
500
50.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8530-01 is: 930
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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REV. B AUGUST 8, 2001
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ICS8530-01
LOW SKEW, 1-TO-16
Integrated
Circuit
Systems, Incꢀ
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
48 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8530DY-01
ICS8530DY-01T
ICS8530DY-01
ICS8530DY-01
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. B AUGUST 8, 2001
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