ICS853001AM [ICSI]
1:1, DIFFERENTIAL LVPECL-TO-2.5V, 3.3V, 5V LVPECL/ECL BUFFER; 1 ： 1 ，差分LVPECL - TO- 2.5V ， 3.3V ， 5V LVPECL / ECL缓冲液
| 型号： | ICS853001AM |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1:1, DIFFERENTIAL LVPECL-TO-2.5V, 3.3V, 5V LVPECL/ECL BUFFER |
| 文件： | 总16页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853001 is a 1:1 Differential LVPECL- • 1:1 Differential LVPECL-to-LVPECL / ECL buffer
ICS
to-LVPECL Buffer and a member of the
• 1 LVPECL clock output pair
HiPerClockS™
HiPerClockS™family of High Performance
Clock Solutions from ICS. The ICS853001
may be used to regenerate LVPECL clocks which
• 1 Differential LVPECL PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
may have been attenuated, across a long trace, or may also
be used as a differential-to-LVPECL translator.The differen-
tial input can accept the following differential input types:
LVPECL, LVDS and CML. The device also has an output en-
able pin for debug/test purposes.When the output is disabled,
it drives differential LOW (Q = LOW, nQ = HIGH). The
ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP
or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on
space-constrained boards.
• Maximum output frequency: >2.5GHz
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
D
Q
VCC
Q
OE
1
2
3
4
8
7
6
5
PCLK
nPCLK
VBB
nQ
VEE
LE
Q
PCLK
ICS853001
8-LeadTSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
nQ
nPCLK
TopView
VBB
ICS853001
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
853001AG
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REV. A JANUARY 29, 2005
1
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCC
Type
Description
1
2, 3
4
Power
Output
Power
Output
Positive supply pin.
Q, nQ
VEE
Differential output pair. LVPECL interface levels.
Negative supply pin.
5
VBB
Nominal bias voltage at VCC - 1.38V.
Pullup/ Inverting differential LVPECL clock input. VCC/2 default when left
Pulldown floating. Can accept LVPECL, LVDS, CML interface levels.
6
7
nPCLK
PCLK
Input
Input
Non-inverting differential LVPECL clock input.
Pulldown
Can accept LVPECL, LVDS, CML interface levels.
Active HIGH output enable. When logic HIGH, the output is enabled
8
OE
Input
Pullup
and follows the input clock. When logic LOW, the output drives logic
low (Q=LOW, nQ=HIGH). LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
37.5
37.5
KΩ
KΩ
RPULLUP
Input Pullup Resistor
853001AG
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REV. A JANUARY 29, 2005
2
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG
-65°C to 150°C
PackageThermal Impedance, θJA
8 Lead TSSOP
8 Lead SOIC
101.7°C/W (0 m/s)
112.7°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
5.25
27
V
mA
TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
0.7VCC
-0.3
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
OE
OE
OE
OE
VCC + 0.3
0.3VCC
150
V
V
Input Low Voltage
Input High Current
Input Low Current
VCC = VIN
VCC = VIN
µA
µA
IIL
-150
TABLE 3C. LVCMOS DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
0.3VEE
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
OE
OE
OE
OE
0.3
0.7VEE
150
V
V
Input Low Voltage
Input High Current
Input Low Current
VEE - 0.3
VCC = VIN
VCC = VIN
µA
µA
IIL
-150
853001AG
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REV. A JANUARY 29, 2005
3
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 5.25V; VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN
Minimum
Typical
Maximum Units
PCLK
200
200
µA
µA
µA
µA
V
nPCLK
PCLK
VCC = VIN
VCC = 5.25, VIN = 0V
VCC = 5.25V, VIN = 0V
-200
-200
0.15
1.2
IIL
Input Low Current
nPCLK
VPP
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak Output Voltage Swing
Bias Voltage
1.2
VCC
VCMR
VOH
V
VCC - 1.005
VCC - 1.78
V
VOL
V
VSWING
VBB
0.6
1.0
V
VCC - 1.44 VCC - 1.38 VCC - 1.32
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375 TO 5.25V; VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
>2.5
500
100
GHz
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
250
tsk(pp)
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz, Integration Range:
12KHz - 20MHz
tjit
0.03
ps
tR / tF
Output Rise/Fall Time
20% to 80%
50
48
250
52
ps
%
V
CC = 2.375V to 3.6V, VEE = 0
VCC > 3.6V to 5.25V, VEE = 0 or
EE = -5.25V to -3.6V,VCC = 0
All parameters are measured at IJ 1.7GHz, unless otherwise noted.
odc
Output Duty Cycle
IJ 1GHz
46
54
%
V
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
853001AG
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REV. A JANUARY 29, 2005
4
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.03ps typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853001AG
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REV. A JANUARY 29, 2005
5
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK
PCLK
VEE
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
-3.25V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK
PCLK
nQ
nQx
PART 1
Qx
nQy
PART 2
Qy
Q
tPD
tsk(pp)
PART-TO-PART SKEW
80%
PROPAGATION DELAY
nQ
80%
tF
Q
VSWING
20%
Pulse Width
Clock
20%
tPERIOD
Outputs
tR
tPW
tPERIOD
odc =
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
853001AG
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REV. A JANUARY 29, 2005
6
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 1A shows an example of the differential input that can
be wired to accept single ended LVCMOS levels.The reference
voltage level VBB generated from the device is connected to
the negative input.The C1 capacitor should be located as close
as possible to the input pin.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1B shows an example of the differential input that can
be wired to accept single ended LVPECL levels.The reference
voltage level VBB generated from the device is connected to
the negative input.
VCC
C1
0.1u
CLK_IN
PCLK
VBB
nPCLK
FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
853001AG
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REV. A JANUARY 29, 2005
7
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V ground level. The R3 in Figure 2B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 2C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 2C. 2.5V LVPECLTERMINATION EXAMPLE
853001AG
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REV. A JANUARY 29, 2005
8
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termina-
tion.Figure 4A shows standard termination for 5V LVPECL.The
termination requires matched load of 50Ω resistors pull down to
VCC - 2V = 3V at the receiver.Figure 4B showsThevenin equiva-
lence of Figure 4A. In actual application where the 3V DC power
supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
R4
84
PECL
Zo = 50 Ohm
Zo = 50 Ohm
PECL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
PECL
PECL
R1
125
R2
125
R1
50
R2
50
3V
FIGURE 4A. STANDARD 5V PECL OUTPUT TERMINATION
FIGURE 4B. 5V PECL OUTPUT TERMINATION EXAMPLE
853001AG
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REV. A JANUARY 29, 2005
9
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with the
and VCMR input requirements. Figures 5A to 5F show interface vendor of the driver component to confirm the driver termina-
examples for the HiPerClockS PCLK/nPCLK input driven by tion requirements.
the most common driver types.The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
125
125
C1
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
VBB
PCLK
C2
nPCLK
nPCLK
HiPerClockS
Input
PCLK/nPCLK
LVPECL
R5
100 - 200
R6
100 - 200
R1
50
R2
50
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
R4
120
120
C1
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
VBB
C2
nPCLK
Zo = 50 Ohm
nPCLK
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 5F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
853001AG
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REV. A JANUARY 29, 2005
10
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
APPLICATION SCHEMATIC EXAMPLE
one termination example is shown in this schematic. For more
termination approaches, please refer to the LVPECL Termina-
tion Application Note.
Figure 6 shows an example of ICS853001 application schematic.
In this example, the device is operated at VCC = 3.3V. The
decoupling capacitor should be located as close as possible to
the power pin.The input is driven by a 3.3V LVPECL driver.Only
VCC
VCC
VCC
R7
R5
R3
R1
133
133
U1
ICS853001
133
133
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
5
6
7
8
4
3
2
1
VBB
VEE
nQ
Q
-
nPCLK
PCLK
OE
VCC
VCC
+
LVPECL
C5
0.1u
R8
R6
82.5
82.5
R4
82.5
R2
82.5
VCC=3.3V
FIGURE 6. APPLICATION SCHEMATIC EXAMPLE
853001AG
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REV. A JANUARY 29, 2005
11
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853001 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5V + 5% = 5.25V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 5.25V * 27mA = 141.75mW
Power (outputs)MAX = 27.83mW/Loaded Output pair
Total Power_MAX (3.465V) = 141.75mW + 27.83mW = 169.58mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = junction-to-ambient thermal resistance
Pd_total =Total device power dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.170W * 90.5°C/W = 100.4°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853001AG
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REV. A JANUARY 29, 2005
12
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.005V
OH_MAX
CC_MAX
)
= 1.005
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.78V
OL_MAX
CC_MAX
)
= 1.78V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1.005V)/50Ω] * 1.005V = 20mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.78V)/50Ω] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
853001AG
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REV. A JANUARY 29, 2005
13
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
RELIABILITY INFORMATION
TABLE 6A θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 6B. θJAVS. AIR FLOW TABLE 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853001 is: 141
853001AG
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REV. A JANUARY 29, 2005
14
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7A. PACKAGE DIMENSIONS
TABLE 7B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUN
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.10
0.15
0.97
0.38
0.23
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
1.27 BASIC
E1
e
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e1
L
L
0.40
0°
0.80
8°
α
α
Reference Document: JEDEC Publication 95, MS-012
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
853001AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 29, 2005
15
ICS853001
Integrated
Circuit
Systems, Inc.
1:1, DIFFERENTIAL LVPECL-TO
-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853001AG
Marking
001A
Package
8 lead TSSOP
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853001AGT
ICS853001AGLF
ICS853001AGLFT
ICS853001AM
001A
8 lead TSSOP
2500 tape & reel
tube
01AL
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
8 lead SOIC
01AL
2500 tape & reel
tube
853001A
853001A
ICS853001AMT
8 lead SOIC
2500 tape & reel
tube
ICS853001AMLF
ICS853001AMLFT
853001AL
853001AL
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
2500 tape & reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853001AG
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REV. A JANUARY 29, 2005
16
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