ICS853006 [ICSI]
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER; 差分至2.5V / 3.3V LVPECL / ECL扇出缓冲器
| 型号： | ICS853006 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER |
| 文件： | 总16页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853006 is a low skew, high performance • 6 differential LVPECL outputs
ICS
1-to-6 Differential-to-2.5V/3.3V LVPECL/ECL
• 1 differential PCLK, nPCLK input pair
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS.The ICS853006 is characterized to operate
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
from a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853006 ideal
for those applications demanding well defined performance
and repeatability.
• Maximum output frequency: > 2GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 510ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
PCLK
nPCLK
VCC
nQ0
Q0
nQ1
Q1
nQ2
Q2
VCC
Q0
nQ0
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
VCC
Q5
nQ5
Q4
nQ4
Q3
nQ3
VCC
VEE
Q1
nQ1
VBB
Q2
nQ2
9
10
PCLK
nPCLK
Q3
nQ3
VBB
Q4
nQ4
ICS853006
20-LeadTSSOP
Q5
nQ5
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
853006AG
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REV. A AUGUST 18, 2004
1
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 8, 13, 20
2, 3
Name
VCC
Type
Description
Power
Output
Output
Output
Input
Positive supply pins.
nQ0, Q0
nQ1, Q1
nQ2, Q2
PCLK
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
4, 5
6, 7
9
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
10
nPCLK
Input
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
11
VBB
Output
Power
Output
Output
Output
Bias voltage.
12
VEE
Negative supply pin.
14, 15
16, 17
18, 19
nQ3, Q3
nQ4, Q4
nQ5, Q5
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
RPULLDOWN Input Pulldown Resistor
75
50
KΩ
KΩ
RVCC/2
Input Pullup/Pulldown Resistor
TABLE 3. CLOCK INPUT FUNCTION TABLE
Input
Outputs
nQ0:nQ5
HIGH
Input to Output Mode
Polarity
PCLK
nPCLK
Q0:Q5
LOW
HIGH
LOW
HIGH
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
LOW
0
Biased; NOTE 1
HIGH
1
Biased; NOTE 1
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853006AG
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REV. A AUGUST 18, 2004
2
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 73.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.465
115
V
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Typ
Max
Min
Max
2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
2.075
1.43
1.86
150
2.36 2.075
1.765 1.43
2.36 2.075
1.765 1.43
2.36
1.765
1.98
VIL
1.98
1.86
150
1.98
1.86
150
VBB
VPP
800
1200
800
1200
800
1200
m
V
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
3.3
1.2
3.3
1.2
3.3
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
-10
-10
µA
µA
PCLK
-10
Input
Low Current
IIL
-150
-150
nPCLK
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853006AG
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REV. A AUGUST 18, 2004
3
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565
0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
1.275
0.63
150
1.56 1.275
0.965 0.63
1.56 1.275
0.965 0.63
-0.83
0.965
1200
800
1200
2.5
150
1.2
800
1200
2.5
150
1.2
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
2.5
V
VCMR
IIH
Input
150
150
150
µA
PCLK0, nPCLK
High Current
-10
-10
-10
µA
µA
PCLK
Input
Low Current
IIL
-150
-150
-150
nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
-40°C
Typ Max
25°C
Typ Max
85°C
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
Typ Max
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.32
1200
-1.005
-1.78
-0.93
-1.685
-0.94
-1.535
-1.32
1200
-0.97
-0.935
-1.67
-0.94
-1.535
-1.32
1200
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
VIL
VBB
VPP
800
800
800
mV
Input High Voltage
Common Mode Range; NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
-10
-10
-10
µA
µA
PCLK
Input
Low Current
IIL
-150
-150
-150
nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853006AG
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REV. A AUGUST 18, 2004
4
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.465V OR VCC = 2.375 TO 3.465V; VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
fMAX
Output Frequency
>2
340 400
15
>2
350 410
15
>2
390 450
17
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
460
27
470
27
510
30
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
150
150
150
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.03
0.03
0.03
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
95
150
205
95
150
205
95
150
205
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853006AG
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REV. A AUGUST 18, 2004
5
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.03ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853006AG
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REV. A AUGUST 18, 2004
6
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK
LVPECL
VEE
VPP
VCMR
Cross Points
PCLK
VEE
nQx
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQx
Qx
PART 1
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
PCLK
80%
tF
80%
VSWING
20%
Clock
20%
nQ0:nQ5
Outputs
tR
Q0:Q5
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
853006AG
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REV. A AUGUST 18, 2004
7
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
The C1 capacitor should be located as close as possible to the
input pin.
VBB generated from the device is connected to the negative input.
VCC
C1
0.1u
CLK_IN
PCLK
VBB
nPCLK
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
853006AG
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REV. A AUGUST 18, 2004
8
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853006AG
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REV. A AUGUST 18, 2004
9
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with
and VCMR input requirements. Figures 4A to 4F show interface the vendor of the driver component to confirm the driver ter-
examples for the HiPerClockS PCLK/nPCLK input driven by mination requirements.
the most common driver types.The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
R1
100
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
125
125
C1
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
VBB
PCLK
C2
nPCLK
nPCLK
HiPerClockS
Input
PCLK/nPCLK
LVPECL
R5
100 - 200
R6
100 - 200
R1
50
R2
50
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
F
IGURE 4D. H
I
P
ER
C
LOCKS PCLK/nPCLK INPUT
D
RIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
R4
120
120
C1
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
VBB
C2
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
853006AG
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REV. A AUGUST 18, 2004
10
ICS853006
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
SCHEMATIC EXAMPLE
Additional LVPECL driver termination approaches are shown in
the LVPECL Termination Application Note. It is recommended
at least one decoupling capacitor per power pin.The decoupling
capacitors should be physically located near the power pins.
For ICS853006, the unused output can be left floating.
Figure 5 shows a schematic example of ICS853006. The
ICS853006 input can accept various types of differential input
signal. In this example, the inputs are driven by an LVPECL driv-
ers. For the ICS853006 LVPECL output driver, an example of
LVPECL driver termination approach is shown in this schematic.
Zo = 50
+
Zo = 50
-
R2
50
R1
50
3.3V
U1
ICS853006
R3
50
C5 (Optional)
0.1u
3.3V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
nQ0
Q0
nQ1
Q1
nQ2
Q2
VCC
PCLK
nPCLK
VCC
Q5
nQ5
Q4
nQ4
Q3
nQ3
VCC
VEE
VBB
3.3V
Zo = 50
Zo = 50
+
-
Zo = 50
Zo = 50
R5
50
R4
50
3.3V LVPECL
R9
50
R10
50
(U1, 1)
(U1, 8)
(U1, 13)
(U1, 20)
3.3V
R6
50
C6 (Optional)
0.1u
R11
50
C7(Optional)
0.1u
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
FIGURE 5. ICS853006 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC EXAMPLE
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ICS853006
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LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853006.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853006 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.48mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (3.465V, with all outputs switching) = 398.48mW + 185.64mW = 584.12mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.584W * 66.6°C/W = 123.9°C. This is below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown inFigure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CC_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
= 1.67V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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ICS853006
Integrated
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LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θ byVelocity (Linear Feet per Minute)
JA
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853006 is: 1340
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LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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ICS853006
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LOW
SKEW, 1-TO-6
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853006AG
Marking
Package
Count
72 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
ICS853006AG
ICS853006AG
20 lead TSSOP
ICS853006AGT
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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