ICS853011AM [IDT]
Low Skew Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 X 1.37 MM, SOIC-8;
| 型号： | ICS853011AM |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 X 1.37 MM, SOIC-8 光电二极管 |
| 文件： | 总12页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853011 is a low skew, high perfor- • 2 differential 2.5V/3.3V LVPECL / ECL outputs
mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
ECL Fanout Buffer and a member of the
• 1 differential PCLK, nPCLK input pair
HiPerClockS™
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853011
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853011 ideal for those
clock distribution applications demanding well defined
performance and repeatability.
• Maximum output frequency: 3GHz (typical)
• Translates any single ended input signal to 3.3V
LVPECLlevels with resistor bias on nPCLK input
• Output skew: 5ps (typical)
• Part-to-part skew: 130ps (typical)
• Propagation delay: 240ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100LVEP11 and SY100EP11U
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
Vcc
1
2
3
4
8
7
6
5
Q0
nQ0
PCLK
nPCLK
VEE
PCLK
nPCLK
Q1
nQ1
nQ1
ICS853011
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
1
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
6
nPCLK
PCLK
VCC
Clock input. VCC/2 default when left floating. LVPECL interface levels.
7
Input
Pulldown Clock input. Default LOW when left floating. LVPECL interface levels.
Positive supply pin.
8
Power
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
RPULLDOWN
Input Pulldown Resistor
75
KΩ
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
2
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V
-4.6V
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
Outputs, VO
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 112°C/W (0 lfpm)
(Junction-to-Ambient)
Package Thermal Impedance, θJC 41°C/W to 44°C/W
(Junction-to-Case)
Wave Solder, TSOL
265°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
25
V
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
Symbol Parameter
25°C
Typ
85°C
Units
Min Typ Max
Min
Max Min Typ Max
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Peak-to-Peak Input Voltage
VCC - 0.9
VCC - 1.7
800
V
V
V
V
VOL
VSWING
VPP
0.15
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
VCMR
IIH
VEE + 1.2
V
150
µA
PCLK
Input Low Current
nPCLK
-5
-150
IIL
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than
500 lfpm is maintained.
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
3
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
Symbol Parameter
25°C
Typ
85°C
Units
Min Typ Max
Min
Max Min Typ Max
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Peak-to-Peak Input Voltage
VCC - 0.9
VCC -1.7
0.8
V
V
V
V
VOL
VSWING
VPP
0.15
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
VCMR
IIH
VEE + 1.2
V
150
µA
PCLK
Input Low Current
nPCLK
-5
-150
IIL
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than
500 lfpm is maintained.
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.125V to -1.3V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
-40°C
25°C
Typ
85°C
Symbol Parameter
Units
Min Typ Max
Min
Max Min Typ Max
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
0.8
V
V
V
V
VOL
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Peak-to-Peak Input Voltage
VSWING
VPP
0.15
Input High Voltage
Common Mode Range; NOTE 2, 3
PCLK
Input High Current
nPCLK
VCMR
IIH
VCC + 1.2
V
150
µA
PCLK
Input Low Current
nPCLK
-5
-150
IIL
µA
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than
500 lfpm is maintained.
NOTE: Input and output parameters vary 1:1 with VCC
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
4
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
fMAX
Output Frequency
3
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
TBD
5
tsk(o)
tsk(pp)
tR/tF
20
ps
Part-to-Part Skew; NOTE 3, 4
130
ps
Output Rise/Fall Time
20% to 80%
120
ps
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
5
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V
VCC
SCOPE
Qx
nPCLK
LVPECL
VPP
VCMR
Cross Points
PCLK
VEE
nQx
VEE = -0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
PCLK
80%
80%
VSWING
20%
20%
nQ0, nQ1
Clock Outputs
t
t
F
R
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
6
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF ~ VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1. This bias circuit clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin. The ratio and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECLcompatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
7
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853011.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853011 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 25mA= 95mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.8V, with all outputs switching) = 95mW + 60.4mW = 155.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.155W * 103.3°C/W = 101°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE qJA FOR 8-PIN SOIC, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
8
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
9
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853011 is: 96
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
10
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
11
PRELIMINARY
ICS853011
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853011AM
Marking
853011A
853011A
Package
8 lead SOIC
Count
96 per tube -40°C to 85°C
2500 -40°C to 85°C
Temperature
ICS853011AMT
8 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
12
相关型号：
ICS853011AMLF
Low Skew Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 X 1.37 MM, SOIC-8
IDT
ICS853011AMLFT
Low Skew Clock Driver, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 X 1.37 MM, SOIC-8
IDT
ICS853011BG
Low Skew Clock Driver, 853011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8
IDT
ICS853011BGLFT
Low Skew Clock Driver, 853011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8
IDT
ICS853011BGT
Low Skew Clock Driver, 853011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8
IDT
ICS853011CGLF
Low Skew Clock Driver, 853011 Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8
IDT
©2020 ICPDF网 联系我们和版权申明