ICS853011CG [ICSI]
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER; 低偏移， 1到2差分至2.5V / 3.3V LVPECL / ECL扇出缓冲器
| 型号： | ICS853011CG |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER |
| 文件： | 总14页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
GENERAL DESCRIPTION
FEATURES
The ICS853011C is a low skew, high perfor- • 2 differential 2.5V/3.3V LVPECL / ECL outputs
ICS
mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
• 1 differential PCLK, nPCLK input pair
HiPerClockS™
ECL Fanout Buffer and a member of the
HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The ICS853011C
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853011C ideal for those
clock distribution applications demanding well defined
performance and repeatability.
• Output frequency: 3GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Output skew: 5ps (typical)
• Part-to-part skew: TBD
• Propagation delay: 250ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100LVEP11 and SY100EP11U
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
Vcc
1
2
3
4
8
7
6
5
Q0
nQ0
PCLK
nPCLK
VEE
PCLK
nPCLK
Q1
nQ1
nQ1
ICS853011C
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
ICS853011C
8-LeadTSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853011CM
www.icst.com/products/hiperclocks.html
REV. A MARCH 19, 2004
1
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
3, 4
5
Pullup/
Pulldown
6
nPCLK
Input
Clock input. LVPECL interface levels.
7
8
PCLK
VCC
Input
Pulldown Clock input. Default LOW when left floating. LVPECL interface levels.
Positive supply pin.
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
75
37
KΩ
KΩ
RPULLUP
Input Pullup Resistor
853011CM
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REV. A MARCH 19, 2004
2
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 112.7°C/W (0 lfpm)
(Junction-to-Ambient) for 8 Lead SOIC
PackageThermal Impedance, θJA 101.7°C/W (0 m/s)
(Junction-to-Ambient) for 8 Lead TSSOP
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.8
V
18
mA
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
2.275
1.545
800
Max
Min
Typ
2.295
1.52
800
Max
Min
Max
2.295
V
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
1.535
800
Input High Voltage
Common Mode Range; NOTE 2, 3
V
VCMR
IIH
Input
µA
PCLK, nPCLK
High Current
µA
µA
PCLK
Input
Low Current
IIL
nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853011CM
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REV. A MARCH 19, 2004
3
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
1.475
0.745
800
Max
Min
Max
Min
Max
1.495
1.495
V
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
0.72
800
0.735
800
Input High Voltage
Common Mode Range; NOTE 2, 3
V
VCMR
IIH
Input
µA
PCLK, nPCLK
High Current
µA
µA
PCLK
Input
Low Current
IIL
nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 3D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
-40°C
Typ Max
25°C
Typ Max
85°C
Symbol Parameter
Units
Min
Min
Min
Typ Max
-1.005
-1.025
-1.755
800
-1.005
-1.78
800
V
V
V
VOH
VOL
VPP
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
800
Input High Voltage
Common Mode Range; NOTE 2, 3
V
VCMR
IIH
Input
µA
PCLK, nPCLK
High Current
µA
µA
Input
PCLK
IIL
Low Current nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
-40°C
Min Typ
25°C
Min Typ
85°C
Symbol Parameter
Units
Max
Max
Min Typ
Max
fMAX
Output Frequency
3
240
5
3
250
5
3
260
5
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
tsk(o)
tsk(pp)
tR/tF
ps
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time 20% to 80%
ps
160
50
160
50
160
50
ps
odc
Output Duty Cycle
f ≤ 1GHz
%
All parameters are measured at f ≤ 1.7GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853011CM
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REV. A MARCH 19, 2004
4
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK
LVPECL
VPP
VCMR
Cross Points
PCLK
VEE
nQx
VEE
-1.8V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
PCLK
80%
tF
80%
VSWING
20%
nQ0, nQ1
Clock
20%
Outputs
tR
Q0, Q1
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
853011CM
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REV. A MARCH 19, 2004
5
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
853011CM
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REV. A MARCH 19, 2004
6
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER
T
ERMINATION
EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER
T
ERMINATION
E
XAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
-
Zo = 50 Ohm
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853011CM
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REV. A MARCH 19, 2004
7
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with the
and VCMR input requirements. Figures 4A to 4E show interface vendor of the driver component to confirm the driver termina-
examples for the HiPerClockS PCLK/nPCLK input driven by tion requirements.
the most common driver types.The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
R1
120
R2
120
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853011CM
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REV. A MARCH 19, 2004
8
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853011C.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853011C is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 18mA = 68.4mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 68.4mW + 61.88mW = 130.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W perTable 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.130W * 103.3°C/W = 98.4°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5A. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 5B. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
853011CM
www.icst.com/products/hiperclocks.html
REV. A MARCH 19, 2004
9
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
–0.935V
OH_MAX
CC_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
= 1.67V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853011CM
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REV. A MARCH 19, 2004
10
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
RELIABILITY INFORMATION
TABLE 6A. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 6B. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS853011C is: 96
853011CM
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REV. A MARCH 19, 2004
11
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
853011CM
www.icst.com/products/hiperclocks.html
REV. A MARCH 19, 2004
12
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.10
0.15
0.97
0.38
0.23
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
E1
e
e1
L
0.40
0°
0.80
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
853011CM
www.icst.com/products/hiperclocks.html
REV. A MARCH 19, 2004
13
PRELIMINARY
ICS853011C
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-2
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
B
UFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853011CM
Marking
853011C
853011C
3011CLF
3011CLF
011C
Package
Count
96 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
8 lead SOIC
ICS853011CMT
ICS853011CMLF
ICS853011CMLFT
ICS853011CG
8 lead SOIC on Tape and Reel
"Lead Free" 8 lead SOIC
96 per tube
2500
"Lead Free" 8 lead SOIC on Tape and Reel
8 lead TSSOP
96 per tube
2500
ICS853011CGT
011C
8 lead TSSOP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853011CM
www.icst.com/products/hiperclocks.html
REV. A MARCH 19, 2004
14
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