ICS853013AMLF [ICSI]
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER; 低歪曲率，双通道， 1 - TO- 3 ，差分至2.5V / 3.3V / 5V LVPECL / ECL扇出缓冲器
| 型号： | ICS853013AMLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER |
| 文件： | 总17页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS853013 is a low skew, high perfor- • Two differential LVPECL / ECL bank outputs
ICS
HiPerClockS™
mance dual 1-to-3 Differential-to-2.5V/3.3V/5V
• Two differential LVPECL clock input pairs
LVPECL/ECL Fanout Buffer and a member of
the HiperclocksTM family of High Performance
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Clock Solutions from ICS. The ICS853013
operates with a positive or negative power supply at 2.5V,
3.3V, or 5V. Guaranteed output and part-to-part skew
characteristics make the ICS853013 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
• Output frequency: >2GHz (typical)
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Output skew: 40ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 570ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
QA1
nQA1
QA2
nQA2
VCC
QB2
nQB2
QB1
nQB1
VEE
nQA0
QA0
VCC
PCLKA
nPCLKA
PCLKB
nPCLKB
VCC
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
nQA0
PCLKA
nPCLKA
QA1
nQA1
QA2
nQA2
nQB0
QB0
9
10
QB0
nQB0
PCLKB
ICS853013
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
nPCLKB
QB1
nQB1
QB2
nQB2
Top View
853013AM
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REV.A OCTOBER 19, 2005
1
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQA0, QA0
VCC
Type
Description
Output
Power
Input
Differential output pair. LVPECL interface levels.
Power supply pins.
3, 8, 16
4
PCLKA
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
5
6
7
nPCLKA
PCLKB
Input
Input
Input
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
nPCLKB
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
9, 10
11
nQB0, QB0
VEE
Output
Power
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Negative supply pin.
12, 13
14, 15
17, 18
19, 20
nQB1, QB1
nQB2, QB2
nQA2, QA2
nQA1, QA1
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
RPULLDOWN Input Pulldown Resistor
RVCC/2 Pullup/Pulldown Resistors
Parameter
Test Conditions
Minimum
Typical
75
Maximum
Units
kΩ
50
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
PCLKA or
PCLKB
nPCLKA or
nPCLKB
QA0:QA2,
QB0:QB2
nQA0:nQA2,
nQB0:nQB2
0
1
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
HIGH
HIGH
LOW
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
853013AM
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REV.A OCTOBER 19, 2005
2
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
5.5V (LVPECL mode, VEE = 0)
-5.5V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 46.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 5.25V; VEE = 0V
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Power Supply Voltage
Power Supply Current
2.375
3.3
5.25
60
V
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Typ
Max
Min
Max
2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
2.075
1.43
150
2.36 2.075
1.765 1.43
2.36 2.075
1.765 1.43
2.36
1.765
1200
800
1200
3.3
150
1.2
800
1200
3.3
150
1.2
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
3.3
V
VCMR
IIH
Input
PCLKA, PCLKB
150
150
150
µA
High Current nPCLKA, nPCLKB
-10
-10
µA
µA
PCLKA, PCLKB
-10
Input
Low Current
IIL
-150
-150
nPCLKA, nPCLKB
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB
is VCC + 0.3V.
853013AM
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REV.A OCTOBER 19, 2005
3
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565
0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
1.275
0.63
150
1.56 1.275
0.965 0.63
1.56 1.275
0.965 0.63
-0.83
0.965
1200
800
1200
2.5
150
1.2
800
1200
2.5
150
1.2
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
1.2
2.5
V
VCMR
IIH
Input
PCLKA, PCLKB
150
150
150
µA
High Current nPCLKA, nPCLKB
-10
-10
-10
µA
µA
PCLKA, PCLKB
Input
Low Current
IIL
-150
-150
-150
nPCLKA, nPCLKB
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB
is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
-40°C
Typ Max
25°C
Typ Max
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
Min
-1.075
-1.875
-1.225
-1.87
Min
-1.005
-1.86
-1.225
-1.87
150
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
1200
-1.005
-1.78
-0.93
-1.685
-0.94
-0.97
-0.935
-1.67
-0.94
-1.535
1200
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
-1.535
1200
150
800
150
800
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
PCLKA, PCLKB
150
150
150
µA
High Current nPCLKA, nPCLKB
-10
-10
-10
µA
µA
PCLKA, PCLKB
Input
Low Current
IIL
-150
-150
-150
nPCLKA, nPCLKB
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKB and PCLKA, nPCLKB
is VCC + 0.3V.
853013AM
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REV.A OCTOBER 19, 2005
4
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
-40°C
25°C
Typ Max
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
Typ Max
Min
-1.075
-1.875
-1.225
-1.87
Min
-1.005
-1.86
-1.225
-1.87
150
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
1200
-1.005
-1.78
-0.93
-1.685
-0.94
-0.97
-0.935
-1.67
-0.94
-1.535
1200
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
-1.765
-1.535
1200
150
800
150
800
800
VPP
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
PCLKA, PCLKB
150
150
150
µA
High Current nPCLKA, nPCLKB
-10
-10
-10
µA
µA
PCLKA, PCLKB
Input
Low Current
IIL
-150
-150
-150
nPCLKA, nPCLKB
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB
is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
-40°C
Typ
>2
25°C
Typ
>2
85°C
Symbol Parameter
Units
Min
Max Min
Max Min
Typ Max
fMAX
Output Frequency
>2
GHz
ps
Propagation Delay, Low-to-High;
NOTE 1
tPLH
300
300
410
410
510
510
330
330
425
425
520 360
520 360
465
465
570
570
Propagation Delay, High-to-Low;
NOTE 1
tPHL
ps
tsk(o)
Output Skew; NOTE 2, 4
40
40
40
40
40
40
ps
ps
ps
tsk(odc) Output Duty Cycle Skew
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
250
250
250
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
0.03
180
0.03
180
0.03
190
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
120
250
140
150
230
All parameters tested ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853013AM
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REV.A OCTOBER 19, 2005
5
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
-50
Input/Output Additive
Phase Jitter at 156.25MHz
= 0.03ps (typical)
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853013AM
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REV.A OCTOBER 19, 2005
6
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
VCC
Qx
VCC
LVPECL
nPCLKA,
nPCLKB
nQx
VPP
VCMR
Cross Points
VEE
PCLKA,
PCLKB
-0.375V to -3.25V
VEE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLKA,
nPCLKB
nPCLKA,
nPCLKB
PCLKA,
PCLKB
PCLKA,
PCLKB
nQA0:nQA2,
nQB0:nQB2,
nQA0:nQA2,
nQB0:nQB2,
QA0:QA2,
QB0:QB2,
QA0:QA2,
QB0:QB2,
tpLH
tpHL
tpLH
OUTPUT DUTY CYCLE SKEW
80%
tpHL
tsk(odc) = ⎥ tpLH - tpHL
⎥
PROPAGATION DELAY
80%
tF
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
853013AM
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REV.A OCTOBER 19, 2005
7
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF ~ VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
PCLK/nPCLK INPUT:
LVPECL OUTPUT
For applications not requiring the use of a differential input, All unused LVPECL outputs can be left floating. We
both the PCLK and nPCLK pins can be left floating. Though recommend that there is no trace attached. Both sides of the
not required, but for additional protection, a 1kΩ resistor can differential output pair should either be left floating or
be tied from PCLK to ground.
terminated.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
853013AM
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REV.A OCTOBER 19, 2005
8
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other suggested here are examples only. If the driver is from an-
differential signals. Both VSWING and VOH must meet the VPP other vendor, use their termination recommendation. Please
and VCMR input requirements. Figures 2A to 2E show inter- consult with the vendor of the driver component to confirm
face examples for the HiPerClockS PCLKx/nPCLKx input the driver termination requirements.
driven by the most common driver types.The input interfaces
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853013AM
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REV.A OCTOBER 19, 2005
9
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termi- ance techniques should be used to maximize operating
nation for LVPECL outputs. The two different layouts men- frequency and minimize signal distortion. Figures 3A and
tioned are recommended only as guidelines.
3B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTT ERMINATION
853013AM
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REV.A OCTOBER 19, 2005
10
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 4C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
853013AM
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REV.A OCTOBER 19, 2005
11
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853013.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853013 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.25V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.25V * 60mA = 315mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (5.25V, with all outputs switching) = 315mW + 185.64mW = 500.64mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.500W * 39.7°C/W = 104.85°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN SOIC, FORCED CONVECTION
θ byVelocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853013AM
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REV.A OCTOBER 19, 2005
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ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
Figure 5. LVPECL Driver Circuit andTermination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
CCO_MAX
OL_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO _MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853013AM
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REV.A OCTOBER 19, 2005
13
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θ byVelocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC StandardTest Boards
Multi-Layer PCB, JEDEC StandardTest Boards
83.2°C/W
65.7°C/W
57.5°C/W
46.2°C/W
39.7°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853013 is: 226
Pin compatible with MC100LVEL13, MC100EL13
853013AM
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REV.A OCTOBER 19, 2005
14
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 20 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
853013AM
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REV.A OCTOBER 19, 2005
15
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS853013AM
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853013AM
ICS853013AM
20 Lead SOIC
ICS853013AMT
ICS853013AMLF
ICS853013AMLFT
20 Lead SOIC
1000 tape & reel
tube
ICS853013AMLF
ICS853013AMLF
20 Lead "Lead-Free" SOIC
20 Lead "Lead-Free" SOIC
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853013AM
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REV.A OCTOBER 19, 2005
16
ICS853013
LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO-
2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free marking.
Rev
Table
T8
Page
8
16
Date
A
10/19/05
853013AM
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REV.A OCTOBER 19, 2005
17
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