ICS85301AGLFT [ICSI]
2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER; 2 ： 1差分至LVPECL多路复用器
| 型号： | ICS85301AGLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER |
| 文件： | 总19页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85301 is a high performance 2:1 Differ- • 2:1 LVPECL MUX
ICS
HiPerClockS™
ential-to-LVPECL Multiplexer and a member of the
• One LVPECL output
HiPerClockS™family of High Performance Clock
Solutions from ICS.The ICS85301 can also per-
form differential translation because the differ-
• Two differential clock inputs can accept: LVPECL, LVDS,
CML
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85301 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
• Maximum input/output frequency: 3GHz
• Translates LVCMOS/LVTTL input signals to LVPECL levels
by using a resistor bias network on nPCLK0, nPCLK0
• Propagation delay: 490ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Additive phase jitter, RMS: 0.009ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PCLK0
nPCLK0
0
16 15 14 13
PCLK0
1
2
12
VEE
Q
Q
nQ
nPCLK0
11
PCLK1
nPCLK1
1
PCLK1
3
4
10 nQ
VEE
nPCLK1
9
5
6
7
8
CLK_SEL
VBB
ICS85301
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
TopView
1
2
3
4
5
6
7
8
PCLK0
nPCLK0
PCLK1
nPCLK1
VBB
16
15
14
13
12
11
10
9
nc
VEE
VEE
VCC
VEE
Q
CLK_SEL
nc
nQ
VEE
VCC
ICS85301
16-LeadTSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
TopView
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
PCLK0
Input
Input
Input
Input
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
2
3
4
nPCLK0
PCLK1
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
nPCLK1
Inverting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
5
VBB
nc
Output
Bias voltage.
No connect.
7, 16
Unused
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
Pulldown When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
6
CLK_SEL
Input
8, 13
9, 12, 14, 15
10, 11
VCC
VEE
Power
Power
Output
Positive supply pins.
Negative supply pins.
nQ, Q
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
1
RPULLUP
37
37
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input
Input Selected
PCLK
CLK_SEL
0
1
PCLK0, nPCLK0
PCLK1, nPCLK1
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2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
16 VFQFN
16TSSOP
JA
51.5°C/W (0 lfpm)
89°C/W (0 lfpm)
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
26
V
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
2.5
2.625
24
V
mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage CLK_SEL
2
VCC + 0.3
0.8
V
V
Input Low Voltage CLK_SEL
Input High Current CLK_SEL
Input Low Current CLK_SEL
-0.3
VCC = VIN = 3.465V or 2.625V
150
µA
µA
IIL
VCC = 3.465V or 2.625V, VIN = 0V
-150
NOTE: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information, "Output Load Test Circuit".
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465
Minimum Typical Maximum Units
PCLK0, nPCLK0,
PCLK1, nPCLK1
150
µA
PCLK0, PCLK1
VCC = 3.465V, VIN = 0V
-10
-150
150
µA
µA
mV
V
IIL
Input Low Current
nPCLK0, nPCLK1
VCC = 3.465V, VIN = 0V
VPP
VCMR
VOH
VOL
VBB
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Bias Voltage
1200
3.3
1.2
2.01
1.24
1.695
2.535
1.845
2.145
V
V
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V. .
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCC = VIN = 2.625V
VCC = 2.625V, VIN = 0V
Minimum Typical Maximum Units
Input High
Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
IIH
150
µA
PCLK0, PCLK1
-10
-150
150
µA
µA
mV
V
IIL
Input Low Current
nPCLK0, nPCLK1
VCC = 2.625V, VIN = 0V
VPP
VCMR
VOH
VOL
VBB
Peak-to-Peak Input Voltage
1200
2.5
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Bias Voltage
1.2
1.25
0.48
0.935
1.705
1.005
1.305
V
V
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V. .
TABLE 5A. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
3
GHz
ps
tPD
240
490
150
25
tsk(pp)
tsk(i)
ps
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
622MHz (Integration Range:
12KHz - 20MHz)
tjit
0.009
-55
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
100
48
200
52
ps
ꢀ
MUX_ISOL MUX Isolation
f = 622MHz
dBm
All parameters measured at f ≤ 1.7GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VCC = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
3
GHz
ps
tPD
240
490
150
25
tsk(pp)
tsk(i)
ps
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
622MHz (Integration Range:
12KHz - 20MHz)
tjit
0.009
-55
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
100
47
200
53
ps
ꢀ
MUX_ISOL MUX Isolation
f = 622MHz
dBm
For notes, see Table 5A above.
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Additive Phase Jitter
3.3V or 2.5V @ 622MHz (12KHz to 20MHz)
= 0.009ps typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
2V
SCOPE
SCOPE
VCC
VCC
Qx
Qx
LVPECL
VEE
LVPECL
VEE
nQx
nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VCC
nQx
PART 1
Q0x
nPCLK0,
nPCLK1
nQy
VPP
VCMR
Cross Points
PART 2
Qy
nPCLK0,
nPCLK1
tsk(pp)
VEE
PART-TO-PART SKEW
DIFFERENTIAL INPUT LEVEL
nQ
nPCLK0,
nPCLK1
Q
PCLK0,
PCLK1
tPW
tPERIOD
nQ
tPW
odc =
x 100ꢀ
Q
tPERIOD
tPD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
nPCLK0
PCLK0
80ꢀ
tF
80ꢀ
tR
VOD
Clock
Outputs
20ꢀ
20ꢀ
nPCLK1
PCLK1
nQ
Q
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2
|
INPUT SKEW
OUTPUT RISE/FALL TIME
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
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Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 1A shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level VBB generated from the device is
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 1B shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level VBB generated from the device is
connected to the negative input.
VCC(or VDD)
CLK_IN
PCLK
VBB
nPCLK
FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 2A to 2F show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
125
125
C1
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
VBB
PCLK
C2
nPCLK
nPCLK
HiPerClockS
Input
PCLK/nPCLK
LVPECL
R5
100 - 200
R6
100 - 200
R1
50
R2
50
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
R4
120
120
C1
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
VBB
C2
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
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2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
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Systems, Inc.
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can
be tied from PCLK to ground.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi- ance techniques should be used to maximize operating
nation for LVPECL outputs. The two different layouts men- frequency and minimize signal distortion. Figures 3A and
tioned are recommended only as guidelines.
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
FOUT and nFOUT are low impedance follower outputs that would be recommended that the board designers simulate
generate ECL/LVPECL compatible outputs. Therefore, ter- to guarantee compatibility across all printed circuit and clock
minating resistors (DC current path to ground) or current component process variations.
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTT ERMINATION
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2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 4C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
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APPLICATION SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS85401 application sche- decoupling capacitor should be located as close as possible
matic. This device can accept different types of input signal. to the power pin.
In this example, the input is driven by a LVDS driver. The
3.3V
C1
0.1u
3.3V
Zo = 50
R2
100
Zo = 50
1
2
3
4
12
11
10
9
Zo = 50
Zo = 50
CLK0
nCLK0
CLK1
GND
Q
nQ
+
-
LVDS
R1
nCLK1
GND
100
3.3V
U1
ICS85401
Zo = 50
3.3V
R3
100
R4
1K
C2
0.1u
Zo = 50
LVDS
FIGURE 5. ICS85401 APPLICATION SCHEMATIC EXAMPLE
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Integrated
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85301.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85301 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 26mA = 90.09mW
Power (outputs)MAX = 27.83mW/Loaded Output pair
Total Power_MAX (3.465, with all outputs switching) = 90.09mW + 27.83mW = 117.92mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5°C/W perTable 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.118W * 51.5°C/W = 91.1°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION
θJA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TABLE 6B. THERMAL RESISTANCE θJA FOR FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
85301AK
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.005V
CC_MAX
OH_MAX
)
= 1.005
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.78V
OL_MAX
CC_MAX
)
= 1.78V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1.005V)/50Ω] * 1.005V = 20mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.78V)/50Ω] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
85301AK
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θJA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85301 is: 137
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
0.25
1.25
3.0
E2
L
0.25
0.30
1.25
0.50
Reference Document: JEDEC Publication 95, MO-220
85301AK
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
85301AK
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85301AK
Marking
Package
Shipping Packaging
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
301A
301A
16 Lead VFQFN
ICS85301AKT
ICS85301AKLF
ICS85301AKLFT
ICS85301AG
16 Lead VFQFN
2500 Tape & Reel
Tray
01AL
16 Lead "Lead-Free" VFQFN
16 Lead "Lead-Free" VFQFN
16 Lead TSSOP
01AL
2500 Tape & Reel
tube
85301AG
85301AG
85301AGL
85301AGL
ICS85301AGT
ICS85301AGLF
ICS85301AGLFT
16 Lead TSSOP
2500 tape & reel
Tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85301AK
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ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Ordering Information Table - corrected count.
Rev
A
Table
Page
Date
T9
17
11/17/04
5/23/05
A
Added 16 Lead TSSOP package throughout the datasheet.
10
18
Added Recommendations for Unused Input Pins.
Ordering Information Table - added lead-free marking to ICS85301AGLF
part number.
A
T9
1/16/06
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相关型号：
ICS85301AKLF
Low Skew Clock Driver, 85301 Series, 1 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16
IDT
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