ICS853031 [ICSI]
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER; 低偏移， 1到9差分至2.5V / 3.3V LVPECL / ECL扇出缓冲器
| 型号： | ICS853031 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER |
| 文件： | 总19页 (文件大小：241K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853031 is a low skew, high performance • 9 differential 2.5V/3.3V LVPECL/ECL outputs
ICS
1-to-9 Differential-to-2.5V/3.3V LVPECL/ECL
• Selectable differential CLK, nCLK or LVPECL clock inputs
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS.The ICS853031 has two selectable clock in-
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL,
puts.The CLK, nCLK pair can accept most standard differential
input levels.The PCLK, nPCLK pair can accept LVPECL, LVDS,
CML, or SSTL input levels. The clock enable is internally syn-
chronized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
• PCLK, nPCLK supports the following input types:
LVPECL, LVDS, CML, SSTL
• Output frequency: 1.6GHz (typical)
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to 3.3V LVPECL levels with resistor bias on nCLK or
nPCLK inputs
Guaranteed output skew and part-to-part skew characteristics
make the ICS853031 ideal for high performance workstation
and server applications.
• Output skew: 20ps (typical)
• Part-to-part skew: 75ps (typical)
• Propagation delay: 875ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin compatible with ICS8531-01
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
32 31 30 29 28 27 26 25
LE
CLK
nCLK
PCLK
0
1
VCC
CLK
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCCO
Q3
Q0
nQ0
nPCLK
nCLK
nQ3
Q4
Q1
nQ1
CLK_SEL
PCLK
CLK_SEL
ICS853031
nQ4
Q5
Q2
nQ2
nPCLK
VEE
nQ5
VCCO
Q3
nQ3
CLK_EN
9 10 11 12 13 14 15 16
Q4
nQ4
Q5
nQ5
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q6
nQ6
Y package
TopView
Q7
nQ7
Q8
nQ8
853031AY
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REV. B SEPTEMBER 16, 2004
1
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCC
Type
Description
1
2
3
Power
Input
Input
Core supply pin.
CLK
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
nCLK
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
Pulldown
4
CLK_SEL
Input
When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels.
Pulldown Non-inverting differential LVPECL clock input.
5
6
7
PCLK
nPCLK
VEE
Input
Input
Pullup Inverting differential LVPECL clock input.
Negative supply pin.
Power
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
8
CLK_EN
Input
Pullup
9, 16, 17,
24, 25, 32
VCCO
Power
Output supply pins.
10, 11
12, 13
14, 15
18, 19
20, 21
22, 23
26, 27
28, 29
30, 31
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3 Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
Output
Output
Output
Output
Output
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
Differential output pair. LVPECL interface level.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
50
Maximum
Units
KΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
50
KΩ
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REV. B SEPTEMBER 16, 2004
2
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Sourced
CLK, nCLK
Q0:Q8
Disabled; LOW
Disabled; LOW
Enabled
nQ0:nQ8
0
0
1
1
0
1
0
1
Disabled; HIGH
Disabled; HIGH
Enabled
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ8
Q0:Q8
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
Q0:Q8
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ8
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. B SEPTEMBER 16, 2004
3
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
Negative SupplyVoltage,VEE
Inputs, VI
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
-4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature, TSTG -65°C to 150°C
PackageThermal Impedance, θJA 47.9°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Core Supply Voltage
3.465
3.465
77
V
V
Output Supply Voltage
Power Supply Current
2.375
3.3
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
VIH
VIL
CLK_EN, CLK_SEL
2
3.465
0.8
V
CLK_EN, CLK_SEL
-0.3
V
CLK_EN
CLK_SEL
CLK_EN
VCC = VIN = 3.465V or 2.625V
VCC = VIN = 3.465V or 2.625V
IN = 0V, VCC = 3.465V or 2.625V
10
µA
µA
µA
µA
IIH
Input High Current
150
V
-150
-50
IIL
Input Low Current
CLK_SEL VIN = 0V, VCC = 3.465V or 2.625V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS (CLK, nCLK), VCC = 2.375 TO 3.465V; VEE = 0V
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
150
10
Min
Max
150
10
Min
Max
150
10
µA
µA
µA
µA
V
CLK
IIH
Input High Current
nCLK
CLK
-5
0
-5
0
-50
IIL
Input Low Current
-150
0.15
-150
0.15
-150
0.15
nCLK
1.3
1.3
1.3
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range;
NOTE 1, 2
VEE + 0.7
VCC - 0.85 VEE + 0.7
VCC - 0.85 VEE + 0.7
VCC - 0.85
V
VCMR
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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REV. B SEPTEMBER 16, 2004
4
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 3.3V; VEE = 0V
-40°C 25°C
Typ Max Min Typ
2.175 2.275 2.38 2.225 2.295 2.37
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
VOH
VOL
VPP
Output High Voltage; NOTE 1
2.22 2.295 2.365
V
V
V
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
0.15
1.2
0.8
1.3
VCC
0.15
1.2
0.8
1.3
VCC
0.15
1.2
0.8
1.3
VCC
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
V
PCLK
Input High Current
nPCLK
150
10
150
10
150
10
µA
µA
µA
µA
PCLK
Input Low Current
nPCLK
-50
-50
-50
IIL
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VEE can vary 0.165V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4E. LVPECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 2.5V; VEE = 0V
-40°C
Typ Max Min
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
VOH
VOL
VPP
Output High Voltage; NOTE 1
1.375 1.475 1.58 1.425 1.495 1.57
1.42 1.495 1.565
V
V
V
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83
0.15
1.2
0.8
1.3
VCC
0.15
1.2
0.8
1.3
VCC
0.15
1.2
0.8
1.3
VCC
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
V
PCLK
Input High Current
nPCLK
150
10
150
10
150
10
µA
µA
µA
µA
PCLK
Input Low Current
nPCLK
-10
-10
-10
IIL
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VEE can vary 0.125V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853031AY
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 4F. ECL DC CHARACTERISTICS (PCLK, nPCLK), VCC = 0V; VEE = -2.375V TO -3.465V
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Ma-
x
Min
Min
Max
Min
Max
VOH
VOL
VPP
Output High Voltage; NOTE 1
-1.125
-1.895
0.15
-1.025 -0.92
-1.755 -1.62
-1.075
-1.875
0.15
-1.005
-1.78
0.8
-0.93
-1.685
1.3
-1.08
-1.86
0.15
-1.005 -0.935
V
V
V
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
-1.765
0.8
-1.67
1.3
0.8
1.3
0
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
VEE+1.2
VEE+1.2
0
VEE+1.2
0
V
PCLK
Input High Current
nPCLK
150
10
150
10
150
10
µA
µA
µA
µA
PCLK
Input Low Current
nPCLK
-10
-10
-10
IIL
-150
-150
-150
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.465V OR VCC = 2.375 TO 3.465V; VEE = 0V
-40°C
25°C
85°C
Symbol Parameter
fMAX Output Frequency
tPD
Units
Min Typ Max Min Typ Max Min Typ Max
>1.6 >1.6 >1.6
GHz
ps
PCLK, nPCLK
CLK, nCLK
750 825 900 785 875 965 825 925 1025
820 920 1020 860 960 1060 910 1010 1110
Propagation
Delay; NOTE 1
ps
tsk(o)
Output Skew; NOTE 2, 4
20
60
55
20
75
55
25
75
55
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
Output
150
175
200
ps
tR/tF
odc
20% to 80%
f ≤ 266MHz
266MHz < f ≤ 500MHz 46
100 215 400 100 225 400 100 215
350
ps
Rise/Fall Time
48
52
54
48
46
52
54
48
46
52
54
%
%
Output Duty Cycle
All parameters measured at ≤ 500MHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TYPICAL PHASE NOISE
0
-10
-20
155.52MHz Input/Output
RMS Phase Noise Jitter
12K to 20MHz
-30
-40
-50
-60
-
70
-80
-90
Output Phase Noise: 12k to 20MHz = 339fs
Output Phase Noise: 12k to 20MHz = 286fs
-100
-110
120
-
-130
-140
-150
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. B SEPTEMBER 16, 2004
7
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
VCCO
,
Qx
nCLK, nPLK
VPP
LVPECL
VEE
VCMR
Cross Points
CLK, PLK
nQx
VEE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK,
nPLK
80%
tF
80%
CLK,
PLK
VSWING
20%
nQ0:nQ8
Clock
20%
Outputs
tR
Q0:Q8
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ8
Q0:Q8
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF ~ VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
Zo = 50Ω
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
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LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V ground level. The R3 in Figure 4B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 4C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER
T
ERMINATION
E
XAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
-
Zo = 50 Ohm
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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ICS853031
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LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 5A to 5E show inter- For example in Figure 5A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B SEPTEMBER 16, 2004
11
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP and use their termination recommendation. Please consult with the
VCMR input requirements. Figures 6A to 6E show interface ex- vendor of the driver component to confirm the driver termina-
amples for the HiPerClockS PCLK/nPCLK input driven by the tion requirements.
most common driver types. The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 6A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 6B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
CLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 6C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 6D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 6E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B SEPTEMBER 16, 2004
12
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 7 shows an example of ICS853031 application schematic. two terminations examples are shown in this schematic. For
In this example, the device is operated at VCC=3.3V. The more termination approaches, please refer to the LVPECL Ter-
decoupling capacitor should be located as close as possible to mination Application Note.
the power pin.The input is driven by a 3.3V LVPECL driver.Only
VCCO = 3.3V
R1
133
R3
133
VCC = 3.3V
VCC = 3.3V
VCCO = 3.3V
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Q0
R11
50
nQ0
C7
0.1uF
R2
82.5
R4
82.5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
VEE
VCCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
VCCO
3.3V
CLK_SEL
Zo = 50 Ohm
Zo = 50 Ohm
CLK_EN
LVPECL
R8
50
R9
50
U1
ICS853031
R10
50
Zo = 50 Ohm
Zo = 50 Ohm
Q8
+
-
nQ8
R5
50
R6
50
(U1-9)
(U1-16) (U1-17) (U1-24) (U1-25) (U1-32)
VCCO
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
R7
50
Optional
Y-Termination
FIGURE 7. ICS853031 SCHEMATIC
E
XAMPLE
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853031.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853031 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 77mA = 266.8mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power_MAX (3.465V, with all outputs switching) = 266.8mW + 278.5mW = 545.3mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.545W * 42.1°C/W = 108°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
Circuit
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LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CCO_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. B SEPTEMBER 16, 2004
15
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θ byVelocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853031 is: 394
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REV. B SEPTEMBER 16, 2004
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ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. B SEPTEMBER 16, 2004
17
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853031AY
Marking
Package
Count
250 per tray -40°C to 85°C
1000 -40°C to 85°C
250 per tray -40°C to 85°C
1000 -40°C to 85°C
Temperature
ICS853031AY
ICS853031AY
ICS853031AYL
32 Lead LQFP
ICS853031AYT
ICS853031AYLF
32 Lead LQFP on Tape and Reel
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP on
Tape and Reel
ICS853031AYLFT
ICS853031AYL
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. B SEPTEMBER 16, 2004
18
ICS853031
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-2.5V/3.3V LVPECL/ECL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T4B
T4C
T4D
4
4
5
LVCMOS Table - changed IIL (CLK_SEL) from -10µA min. to -50µA min.
Differential Table - change IIL (CLK) from -10µA min. to -50µA min.
3.3V LVPECL Table - change VOH @ 85° to 2.22V min. and 2.295V typical from
2.295V min. and 2.33V typical.
Changed IIL (PCLK) from -10µA min. to -50µA min.
B
5
6
2.5V LVPECL Table - change VOH @ 85° to 1.42V min. and 1.495V typical from
1.495V min. and 1.53V typical.
9/10/03
T4E
T4F
ECL Table - change VOH @ 85° to -1.08V min. and -1.005V typical from
-1.005V min. and -0.97V typical.
9
Revised LVPECL Output Termination drawings.
Revised Figure 6D.
12
13
B
B
Added Schematic Layout
8/19/04
9/16/04
2
4
5
T1
T4B
Pin Description Table - changed nCLK & nPCLK Type to Pullup (only).
LVCMOS Table - added 2.625V in Test Conditions.
T4D & E LVPECL DC Characteristics Tables - corrected Note 3.
6
18
T4F
T9
ECL DC Characteristics Tables - corrected Note 3.
Ordering Information Table - added Lead-Free part number.
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REV. B SEPTEMBER 16, 2004
19
相关型号：
ICS85304AG-01LF
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MO-153, TSSOP-20
IDT
ICS85304AG-01LFT
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MO-153, TSSOP-20
IDT
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