ICS85304AG-01 [ICSI]
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER; 低偏移， 1到5差分至3.3V的LVPECL扇出缓冲器
| 型号： | ICS85304AG-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS85304-01 is a low skew, high perfor- • 5 differential 3.3V LVPECLoutputs
mance 1-to-5 Differential-to-3.3V LVPECL fanout
buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS85304-01 has two selectable clock in-
• Selectable CLK, nCLK or LVPECL clock inputs
HiPerClockS™
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
puts. The CLK, nCLK pair can accept most standard differen-
tial input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally syn-
chronized to eliminate runt clock pulses on the outputs dur-
ing asynchronous assertion/deassertion of the clock enable
pin.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS85304-01 ideal for those applications
demanding well defined performance and repeatability.
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 2.1ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
CLK_EN
VCC
D
CLK_EN
Q
LE
CLK
nCLK
PCLK
nPCLK
PCLK
VEE
nCLK
CLK
0
Q0
nQ0
1
nPCLK
Q1
nQ1
CLK_SEL
VCC
CLK_SEL
nQ4
Q2
nQ2
ICS85304-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
Q3
nQ3
G Package
Top View
Q4
nQ4
85304AG-01
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REV. B JULY 13, 2001
1
ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
VCC
Type
Description
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3, 4
5, 6
7, 8
9, 10
11, 18, 20
Positive supply pins. Connect to 3.3V.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
12
CLK_SEL
Input
Pulldown When LOW, selects CLK, nCLK inputs.
LVTTL / LVCMOS interface levels.
13
14
15
16
17
CLK
nCLK
VEE
Input
Input
Power
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Negative supply pin. Connect to ground.
PCLK
nPCLK
Pulldown Non-inverting differential LVPECL clock input.
Pullup
Inverting differential LVPECL clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock
input. When LOW, Q outputs are forced low, nQ outputs are forced
high. LVTTL / LVCMOS interface levels.
19
CLK_EN
Input
Pullup
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK, nCLK
4
4
pF
pF
PCLK, nPCLK
CIN
Input Capacitance
CLK_EN,
CLK_SEL
4
pF
RPULLUP
Input Pullup Resistor
51
51
KΩ
KΩ
RPULLDOWN
Input Pulldown Resistor
85304AG-01
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK, nCLK
Q0 thru Q4
Disabled; LOW
Disabled; LOW
Enabled
nQ0 thru nQ4
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ4
Q0 - Q4
FIGURE 1 - CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or CLK
nPCLK or nPCLK
Q0 thru Q4
LOW
nQ0 thru nQ4
HIGH
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
LOW
HIGH
1
Biased; NOTE 1
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 8, which discusses wiring the differential
input to accept single ended levels.
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
55
V
IEE
mA
TABLE 4B. LVCMOS / LVTTL CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK_EN,
CLK_SEL
CLK_EN,
CLK_SEL
VIH
Input High Voltage
2
3.765
0.8
V
V
VIL
IIH
Input Low Voltage
Input High Current
-0.3
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN = VCC = 3.465V
5
µA
µA
µA
µA
VIN = VCC = 3.465V
150
VCC = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
V
CC = 3.465V, VIN = 0V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
150
nCLK
CLK
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VCC - 0.85
V
NOTE 1: For single ended applications the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical
Maximum Units
PCLK
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nPCLK
PCLK
V
-5
-150
IIL
Input Low Current
nPCLK
VCC = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
VOH
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
0.5
VCC - 0.85
VCC - 1.0
VCC - 1.7
0.85
V
VCC - 1.4
VCC - 2.0
0.6
V
VOL
Output Low Voltage; NOTE 3
V
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
650
2.1
35
MHz
ns
tPD
IJ 650MHz
1.0
tsk(o)
tsk(pp)
tR
ps
150
700
700
52
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
48
ps
tF
Output Fall Time
ps
odc
Output Duty Cycle
50
ps
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85304AG-01
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REV. B JULY 13, 2001
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2V
nQx
VEE =-1.3V ± 0.135V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VCC
CLK, PCLK
VPP
VCMR
Cross Points
nCLK, nPCLK
VEE
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
CLK, PCLK
nCLK, nPCLK
Q0 - Q4
nQ0 - nQ4
tPD
FIGURE 6 - PROPAGATION DELAY
CLK, PCLK, Qx
nCLK, nPCLK, nQx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
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REV. B JULY 13, 2001
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
R2
1K
0.1uF
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85304-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85304-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.57mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 190.57mW + 151mW = 341.57mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.341W * 66.6°C/W = 92.71°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. B JULY 13, 2001
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
3ꢀ Calculations and Equationsꢀ
LVPECL output driver circuit and termination are shown in Figure 9ꢀ
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 9 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load,
and a termination voltage of V - 2V!
CC
Pd_H is power dissipation when the output drives high!
Pd_L is the power dissipation when the output drives low!
Pd_H = [(V
Pd_L = [(V
(V - 2V))/R ]*(V - V
)
OH_MAX
CC
L
CC
OH_MAX
(V - 2V))/R ]*(V - V )
OL_MAX
OL_MAX
CC
L
CC
•
•
For logic high , V = V
= V 1ꢀ0V
OH_MAX CC
OUT
Using V = 3!465, this results in V
= 2ꢀ465V
CC
OH_MAX
For logic low , V = V
= V 1ꢀ7V
CC
OUT
OL_MAX
Using V = 3!465, this results in V
= 1ꢀ765V
CC
OL_MAX
Pd_H = [(2!465V - (3!465V - 2V))/50 Ω]*(3!465V - 2!465V) = 20ꢀ0mW
Pd_L = [(1!765V - (3!465V - 2V))/50 Ω]*(3!465V - 1!765V) = 10ꢀ2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30ꢀ2mW
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114!5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73!2°C/W
98!0°C/W
66!6°C/W
88!0°C/W
63!5°C/W
NOTE: Most modern PCB designs use multi-layered boardsꢀ The data in the second row pertains to most designsꢀ
TRANSISTOR COUNT
The transistor count for ICS85304-01 is: 489
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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ICS85304-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85304AG-01
Marking
Package
Count
72 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS85304AG-01
ICS85304AG-01
20 lead TSSOP
ICS85304AG-01T
20 lead TSSOP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV. B JULY 13, 2001
13
相关型号：
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ICS85304AG-01LFT
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, LEAD FREE, MO-153, TSSOP-20
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