ICS853052AGT [ICSI]
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER; 双LVCMOS / LVTTL到差分2.5V ， 3.3V ， 5V LVPECL多路复用器
| 型号： | ICS853052AGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER |
| 文件： | 总13页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS853052 is a Dual LVCMOS / LVTTL-to- • 1 differential 2.5V, 3.3V or 5V LVPECL output
ICS
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer
and a member of the HiPerClocks™family of High
Performance Clocks Solutions from ICS. The
ICS853052 has two selectable single ended
• 2 selectable LVCMOS/LVTTL clock inputs
• Output frequency: TBD
HiPerClockS™
• Additive phase jitter, RMS: 0.06ps (typical)
• Propagation Delay: 370ps (typical)
clock inputs. The single ended clock input accepts LVCMOS
or LVTTL input levels and translates them to 2.5V, 3.3V or 5V
LVPECL levels.The small outline 8-pin TSSOP or 8-pin SOIC
packages make this device ideal for applications where space,
high performance and low power are important.
• 2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP58
BLOCK DIAGRAM
PIN ASSIGNMENT
nc
Da
VCC
Q
1
2
3
4
8
7
6
5
Da
1
0
nQ
Q
Db
SEL
nQ
VEE
Db
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
SEL
TopView
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
1
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
nc
Type
Description
1
Unused
Input
No connect.
2, 3
Da, Db
Pulldown LVCMOS / LVTTL clock inputs.
Select input pin. When HIGH, selects Da input clock.
4
SEL
Input
Pulldown When Low selects Db input clock.
Single-ended 100H LVPECL interface levels.
5
6, 7
8
VEE
nQ, Q
VCC
Power
Output
Power
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
1
pF
RPULLDOWN
75
KΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
SEL
0
Selected Source
Db
Da
1
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
2
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
-6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 101.7°C/W (0 m/s)TSSOP
112.7°C/W (0 lfpm) SOIC
(Junction-to-Ambient)
TABLE 4A. DC CHARACTERISTICS, VCC = 2.5V;VEE = 0V
-40°C
Typ
21
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Min
Units
Max
Min
Max
Min
Max
IEE
Power Supply Current
mA
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565
0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83
V
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
V
V
VIH
VIL
1.275
0.63
1.56 1.275
0.965 0.63
1.56 1.275
0.965 0.63
-0.83
0.965
150
µA
µA
IIH
IIL
Input High Current
Input Low Current
150
150
150
150
150
Input and output parameters vary 1:1 with VCC
.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V;VEE = 0V
-40°C
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
IEE
Power Supply Current
21
mA
mV
mV
VOH
VOL
Output High Voltage; NOTE 1 2175 2275 2380 2225 2295 2370 2295
2330
1535
2365
1630
Output Low Voltage; NOTE 1
1405 1545 1680 1425 1520 1615 1440
Input High Voltage),
(Single-Ended)
Input Low Voltage,
(Single-Ended)
VIH
VIL
2075
1355
2420 2075
1675 1355
2420 2075
1675 1355
2420
mV
mV
1675
150
IIH
IIL
Input High Current
Input Low Current
150
150
150
150
µA
µA
150
Input and output parameters vary 1:1 with VCC
.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
3
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TABLE 4C. DC CHARACTERISTICS, VCC = 5V;VEE = 0V
-40°C
Typ
21
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Min
Units
Max
Min
Max
Min
Max
IEE
Power Supply Current
mA
mV
mV
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
3875 3975 4105 4080 3925 3995 4070 3995 4065
3105 3245 3380 3125 3220 3315 3140 3235 3330
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
VIH
VIL
3775
3055
4120 3775
3375 3055
4120 3775
3375 3055
4120
mV
mV
3375
150
IIH
IIL
Input High Current
Input Low Current
150
150
150
150
µA
µA
150
Input and output parameters vary 1:1 with VCC
.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V;VEE = -5.5V TO -2.375V
-40°C
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
IEE
Power Supply Current
21
mA
mV
mV
VOH
VOL
Output High Voltage; NOTE 1 -1125 -1025 -920 -1075 -1005 -930 -1005 -970
-935
Output Low Voltage; NOTE 1
-1895 -1755 -1620 -1875 -1780 -1685 -1860 -1765 -1670
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
VIH
VIL
-1225
-1945
-880 -1225
-1625 -1945
-880 -1225
-1625 -1945
-880
mV
mV
-1625
150
IIH
IIL
Input High Current
Input Low Current
150
150
150
150
µA
µA
150
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V;VEE = -5.5V TO -2.375V OR VCC = 2.375V TO 5.5V;VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
fMAX
Output Frequency
TBD
TBD
TBD
GHz
ps
Propagation Delay, Low to High;
NOTE 1
tPLH
TBD
370
TBD
Propagation Delay, High to Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tPHL
tjit
TBD
TBD
370
TBD
TBD
ps
ps
0.06
VPP
Input Voltage Swing (Differential)
TBD
TBD
TBD
180
TBD
TBD
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
4
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Input/Output Additive Phase Jitter
@ 155.52MHz (12KHz to 20MHz)
= 0.06ps typical
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
1k
10k
100k
1M
10M
100M
-190
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
5
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
VCC
Qx
Da Db
nQ
LVPECL
VEE
Q
nQx
tPD
-3.5V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
6
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
APPLICATION INFORMATION
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 1A and Figure 1B show examples of termination for 2.5V ground level. The R3 in Figure 1B can be eliminated and the
LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 1C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 1A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 1B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 1C. 2.5V LVPECL TERMINATION EXAMPLE
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
7
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termina-
tion.Figure 3A shows standard termination for 5V LVPECL.The
termination requires matched load of 50Ω resistors pull down to
VCC - 2V = 3V at the receiver.Figure 3B shows Thevenin equiva-
lence of Figure 3A. In actual application where the 3V DC power
supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
R4
84
PECL
Zo = 50 Ohm
Zo = 50 Ohm
PECL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
PECL
PECL
R1
125
R2
125
R1
50
R2
50
3V
FIGURE 3A. STANDARD 5V PECL OUTPUT TERMINATION
FIGURE 3B. 5V PECL OUTPUT TERMINATION EXAMPLE
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
8
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853052.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853052 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 5.5V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 5.5V * 21mA = 115.5mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
Total Power_MAX (5.5V, with all outputs switching) = 115.5mW + 30.94mW = 146.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.146W * 90.5°C/W = 98.2°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 6B. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
9
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CC_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CC_MAX
)
(V
- V
= 1.67V
CC_MAX
OL_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC _MAX
OH_MAX
L
CC
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
10
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853052 is: 110
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
11
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
MINIMUN
MAXIMUM
N
A
8
N
A
A1
B
C
D
E
e
8
--
1.10
0.15
0.97
0.38
0.23
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
E
1.27 BASIC
E1
e
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e1
L
L
0.40
0°
0.80
8°
α
α
Reference Document: JEDEC Publication 95, MS-012
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-187
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
12
PRELIMINARY
ICS853052
Integrated
Circuit
Systems, Inc.
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853052AG
Marking
Package
8 lead TSSOP
Count
96 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
052A
052A
ICS853052AGT
ICS853052AM
8 lead TSSOP on Tape and Reel
8 lead SOIC
853052A
853052A
96 per tube
2500
ICS853052AMT
8 lead SOIC on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853052AG
www.icst.com/products/hiperclocks.html
REV. A JULY 1, 2004
13
相关型号：
©2020 ICPDF网 联系我们和版权申明