ICS853054 [ICSI]
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER; 4 : 1 ,差分至3.3V或2.5V LVPECL / ECL时钟多路复用器型号: | ICS853054 |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | 4:1, DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER |
文件: | 总15页 (文件大小:205K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS853054 is an 4:1 Differential-to-3.3V or • High speed 4:1 differential multiplexer
ICS
2.5V LVPECL/ECL Clock Multiplexer which
• One differential 3.3V or 2.5V LVPECL output
can operate up to 2.5GHz and is a member of
HiPerClockS™
the HiPerClockS™ family of High Performance
Clock Solutions from ICS.The ICS853054 has 4
• Four selectable differential PCLK, nPCLK inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
selectable differential clock inputs. The PCLKx, nPCLKx in-
put pairs can accept LVPECL, LVDS, CML or SSTL levels.
The fully differential architecture and low propagation
delay make it ideal for use in clock distribution circuits. The
select pins have internal pulldown resistors.The SEL1 pin is
the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00
selects PCLK0, nPCLK0).
• Maximum output frequency: 3.2GHz
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Part-to-part skew: TBD
• Propagation delay: 465ps (typical)
• Additive phase jitter, RMS: 0.238ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
VEE
16
15
14
13
12
11
10
9
VCC
Q
nQ
VEE
nPCLK3
PCLK3
nPCLK2
PCLK2
PCLK0
00
nPCLK0
PCLK1
01
nPCLK1
Q
nQ
PCLK2
nPCLK2
10
11
ICS853054
16-LeadTSSOP
PCLK3
nPCLK3
4.4mm x 5.0mm x 0.92mm package body
G Package
TopView
SEL0
SEL1
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853054AG
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REV.A JANUARY 5, 2006
1
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
1
PCLK0
Input
Input
Input
Input
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
2
3
4
nPCLK0
PCLK1
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK1
Pullup/Pulldown
5, 16
6, 7
8, 13
9
VCC
SEL0, SEL1
VEE
Power
Input
Positive supply pins.
Pulldown
Clock select input pins. LVCMOS/LVTTL interface levels.
Negative supply pin.
Power
Input
PCLK2
Pulldown
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
10
11
nPCLK2
PCLK3
nPCLK3
nQ, Q
Input
Input
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
12
Input
Pullup/Pulldown
14, 15
Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
75
50
kΩ
kΩ
RVDD/2
Pullup/Pulldown Resistosr
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
SEL1
SEL0
Q/nQ
0
0
1
1
0
1
0
1
PCLK0/nPCLK0
PCLK1/nPCLK1
PCLK2/nPCLK2
PCLK3/nPCLK3
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REV.A JANUARY 5, 2006
2
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5V
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 89°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum Units
VCC
ICC
Positive Supply Voltage
Power Supply Current
2.375
3.465
V
61
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
VCC = 3.3V
Minimum Typical Maximum Units
2
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VCC = 2.5V
1.7
-0.3
-0.3
VCC = 3.3V
Input Low Voltage
VCC = 2.5V
0.7
V
CC = VIN = 3.465V,
VCC = VIN = 2.625V
CC = 3.465V, VIN = 0V,
IIH
IIL
Input High Current SEL0, SEL1
Input Low Current SEL0, SEL1
150
µA
µA
V
-150
VCC = 2.625V, VIN = 0V
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter Test Conditions
IIH Input High Current
Minimum
Typical
Maximum Units
PCLK0:PCLK3
nPCLK0:nPCLK3
V
CC = VIN = 3.465V
150
µA
PCLK0:PCLK3
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
-10
-150
0.15
µA
µA
V
IIL
Input Low Current
nPCLK0:nPCLK3
VPP
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1.2
3.3
V
VOH
Output High Voltage Voltage; NOTE 3
Output Low Voltage; NOTE 3
VCC - 1.005
VCC - 1.78
0.8
V
V
V
VOL
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
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REV.A JANUARY 5, 2006
3
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
Symbol Parameter Test Conditions
Minimum
Typical
-1.005
-1.78
Maximum Units
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
V
V
Output Low Voltage; NOTE 1
Input High Voltage
-1.225
-1.87
-0.94
V
V
Input Low Voltage
-1.535
VPP
Peak-to-Peak Input Voltage
800
mV
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
VEE + 1.2
0
V
Input
PCLK0:PCLK3
150
µA
High Current nPCLK0:nPCLK3
PCLK0:PCLK3
-10
µA
µA
Input Low
Current
IIL
nPCLK0:nPCLK3
-150
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V OR VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
3.2
GHz
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz,
12kHz - 20MHz
tjit
0.238
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
465
TBD
200
ps
ps
ps
tsk(pp)
tR / tF
20% to 80%
V
IN 1.6V to 2.4V,
155.52MHz
MUXISOLATION MUX Isolation
-55
dB
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
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REV.A JANUARY 5, 2006
4
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Additive Phase Jitter, RMS
@ 155.52MHz = <0.238ps typical
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853054AG
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REV.A JANUARY 5, 2006
5
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK0:3
PCLK0:3
VPP
VCMR
LVPECL
Cross Points
nQx
VEE
VEE
-1.465V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK0:3
PCLK0:3
nQ
nQx
PART 1
Qx
nQy
PART 2
Qy
Q
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
80%
tF
80%
VOD
Clock
20%
20%
Outputs
tR
OUTPUT RISE/FALL TIME
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REV.A JANUARY 5, 2006
6
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VCC/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVCC= 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
SELECT PINS:
PCLK/nPCLK INPUT:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resister can be used.
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
853054AG
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REV.A JANUARY 5, 2006
7
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 2A to 2E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL IN DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV.A JANUARY 5, 2006
8
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termi- drive 50Ω transmission lines. Matched impedance techniques
nation for LVPECL outputs. The two different layouts men- should be used to maximize operating frequency and mini-
tioned are recommended only as guidelines.
mize signal distortion. Figures 3A and 3B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process varia-
tions.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTTERMINATION
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REV.A JANUARY 5, 2006
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PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 4C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
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REV.A JANUARY 5, 2006
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PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853054.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853054 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 61mA = 211.37mW
Power (outputs)MAX = 27.83mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 211.37mW + 27.83mW = 239.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 meters per second and a multi-layer board, the appropriate value is 81.8°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.239W * 81.8°C/W = 104.6°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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REV.A JANUARY 5, 2006
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PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.005V
CC_MAX
OH_MAX
)
= 1.005
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.78V
OL_MAX
CC_MAX
)
= 1.78V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1.005V)/50Ω] * 1.005V = 20mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.78V)/50Ω] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
853054AG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 5, 2006
12
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853054 is: 326
853054AG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 5, 2006
13
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
A1
A2
b
0.05
0.80
0.19
0.09
4.90
0.15
1.05
0.30
0.20
5.10
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
853054AG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 5, 2006
14
PRELIMINARY
ICS853054
Integrated
Circuit
Systems, Inc.
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS853054AG
ICS853054AGT
ICS853054AGLF
ICS853054AGLFT
853054AG
853054AG
853054AL
853054AL
16 Lead TSSOP
16 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853054AG
www.icst.com/products/hiperclocks.html
REV.A JANUARY 5, 2006
15
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