ICS853111 [ICSI]
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER; 低偏移， 1到10差分至2.5V / 3.3V LVPECL / ECL扇出缓冲器
| 型号： | ICS853111 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853111 is a low skew, high perfor- • 10 differential 2.5V/3.3V LVPECL / ECLoutputs
mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
ECL Fanout Buffer and a member of the
• 2 selectable differential input pairs
HiPerClockS™
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853111
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853111 ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECLlevels with resistor bias on nPCLK input
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: TBD
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP111 and MC100LVEP111
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PCLK0
nPCLK0
0
1
PCLK1
nPCLK1
Q1
nQ1
24 23 22 21 20 19 18 17
VCCO
nQ2
Q2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Q7
Q2
nQ2
nQ7
Q8
CLK_SEL
VBB
Q3
nQ3
nQ1
Q1
ICS853111
nQ8
Q9
Q4
nQ4
nQ0
Q0
nQ9
Q5
nQ5
VCCO
VCCO
1
2
3
4
5
6
7
8
Q6
nQ6
Q7
nQ7
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q8
nQ8
Y Package
Top View
Q9
nQ9
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
1
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Core supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
2
CLK_SEL Input
Pulldown
Pulldown
3
4
PCLK0
Input
Non-inverting differential clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK0
Input Pullup/Pulldown
5
6
VBB
Output
Bias voltage.
PCLK1
Input
Pulldown
Non-inverting differential clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
7
nPCLK1
Input Pullup/Pulldown
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VEE
Power
Power
Negative supply pin.
VCCO
Output supply pins.
nQ9, Q9 Output
nQ8, Q8 Output
nQ7, Q7 Output
nQ6, Q6 Output
nQ5, Q5 Output
nQ4, Q4 Output
nQ3, Q3 Output
nQ2, Q2 Output
nQ1, Q1 Output
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN Input Pulldown Resistor
75
KΩ
Pullup/Pulldown Resistors
50
KΩ
RVCC/2
TABLE 3A. CONTROL INPUT
FUNCTION TABLE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
Inputs
CLKx
nCLKx Q0:Q9 nQ0:Q9
CLK_SEL Selected Source
0
1
1
0
LOW
HIGH
LOW
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
0
1
CLK0, nCLK0
CLK1, nCLK1
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
1
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Single Ended to Differential Non Inverting
Single Ended to Differential Non Inverting
Biased;
NOTE 1
Biased;
NOTE 1
0
1
Single Ended to Differential
Single Ended to Differential
Inverting
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
2
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECLmode, VCC = 0)
-0.5V to VCC + 0.5 V
Negative Supply Voltage, VEE
Inputs, VI (LVPECLmode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 37.8°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
V
TBD
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
Typ Max Min
85°C
Typ
Symbol Parameter
Units
Min Typ Max
Min
2.225
1.425
2.075
1.43
Max
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
2.175 2.275
1.405 1.545
2.075
2.38
1.68
2.36
1.765
1.98
1200
2.295
1.52
2.37
1.615
2.36
2.295
1.44
2.075
1.43
1.86
150
2.33
2.365
1.63
V
V
V
V
V
V
1.535
2.36
VIL
1.43
1.765
1.98
1.765
1.98
VBB
VPP
1.86
1.86
150
1.2
800
150
800
1200
800
1200
Input High Voltage
Common Mode Range; NOTE 3, 4
VCMR
IIH
3.3
1.2
3.3
1.2
3.3
V
PCLK0, PCLK1
Input High Current
150
150
150
µA
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
IIL
-150
-150
-150
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
3
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min Typ Max
Min Typ Max Min
Max
1.565
0.83
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
1.375 1.475
0.605 0.745
1.275
1.58
0.88
1.425 1.495
1.57
0.815
1.56
1.495
0.64
1.275
0.63
150
1.53
V
V
V
V
V
0.625
1.275
0.63
0.72
800
0.735
1.56
-0.8
0.63
0.965
1200
0.965
1200
0.965
1200
VPP
150
1.2
800
150
800
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
2.5
1.2
2.5
1.2
2.5
V
PCLK0, PCLK1
Input High Current
150
150
150
µA
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
IIL
-150
-150
-150
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.125V to -1.3V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
-40°C
Typ Max
25°C
Typ Max
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
Min
-1.075
-1.875
-1.225
-1.87
Min
-1.005
-1.86
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.005
-1.78
-0.93
-1.685
-0.94
-0.97
-0.935
-1.67
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
-1.225
-1.87
-0.94
-1.535
-1.535
Output Voltage Reference;
NOTE 2
-1.486
150
-1.386
1200
-1.486
150
-1.386
1200
-1.486
150
-1.386
1200
V
V
VBB
VPP
800
800
800
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range;
NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
Input
PCLK0, PCLK1
150
150
150
µA
µA
IIH
IIL
High Current nPCLK0, nPCLK1
Input PCLK0, PCLK1
Low Current nPCLK0, nPCLK1
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
4
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
fMAX
Output Frequency
>3
>3
>3
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
660
695
745
tsk(o)
tsk(pp)
tR/tF
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ps
Part-to-Part Skew; NOTE 3, 4
ps
Output Rise/Fall Time
20% to 80%
ps
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
5
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V
VCC
SCOPE
Qx
nCLK0, nCLK1
VPP
LVPECL
VCMR
Cross Points
CLK0, CLK1
nQx
VEE
VEE = -0.375V to -1.8V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0,
nCLK1
80%
80%
CLK0,
CLK1
VSWING
20%
nQ0:nQ9
Clock
20%
Outputs
tF
tR
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
6
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 2A shows an example of the differential input that can
be wired to accept single ended LVCMOS levels. The reference
voltage level VBB generated from the device is connected to
the negative input. The C1 capacitor should be located as close
as possible to the input pin.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can
be wired to accept single ended LVPECL levels. The reference
voltage level VBB generated from the device is connected to
the negative input. The C1 capacitor should be located as close
as possible to the input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
www.icst.com/products/hiperclocks.html
853111AY
REV. D JULY 22, 2003
7
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECLcompatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
➤
VCC - 2V
Zo = 50Ω
RTT
1
3
2
3
2
Zo
RTT =
Zo
Zo
(VOH + VOL / VCC –2) –2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
8
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 4B show examples of termination for 2.5V ground level. The R3 in Figure 4B can be eliminated and the
LVPECL driver. These terminations are equivalent to terminat- termination is shown in Figure 4C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driver
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
9
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
and VCMR input requirements. Figures 5A to 5E show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 5A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
R1
84
R2
84
FIGURE 5C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
F
IGURE 5E. H
IP
ERCLOCKS PCLK/
NPCLK INPUT
D
RIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
10
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using the input is driven by an LVPECL driver. CLK_SEL is set at logic
ICS853111 LVPECL buffer. Figure 6 shows a schematic ex- high to select PCLK0/nPCLK0 input.
ample of the ICS853111 LVPECL clock buffer. In this example,
Zo = 50
+
Zo = 50
-
R2
50
R1
50
VCC
C6 (Option)
0.1u
R3
50
VCC
Zo = 50 Ohm
Zo = 50 Ohm
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
R4
1K
3.3V LVPECL
R9
50
R10
50
U1
C8 (Option)
0.1u
R11
50
ICS853111
VCC
Zo = 50
+
-
VCC=3.3V
Zo = 50
(U1-9)
(U1-16)
(U1-25) (U1-32) (U1-1)
VCC
R8
50
R7
50
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C7 (Option)
0.1u
R13
50
FIGURE 6. EXAMPLE ICS853111 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111 is: 1340
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
11
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
12
PRELIMINARY
ICS853111
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
32 lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS853111AY
ICS853111AYT
ICS853111AY
ICS853111AY
32 lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853111AY
www.icst.com/products/hiperclocks.html
REV. D JULY 22, 2003
13
相关型号：
ICS853111AT-02LFT
Low Skew Clock Driver, 853111 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABA-HD, TQFP-32
IDT
©2020 ICPDF网 联系我们和版权申明