ICS85356AGI [ICSI]
2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER; 2 ： 1 ，差分至3.3V双LVPECL / ECL时钟多路复用器
| 型号： | ICS85356AGI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER |
| 文件： | 总14页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85356I is a dual 2:1 Differential-to-LVPECL • High speed differential multiplexer.
ICS
Multiplexer and is a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS.The device has both common select and indi-
vidual select inputs.When COM_SEL is logic High,
The device can be configured as a 2:1 multiplexer
HiPerClockS™
• Dual 3.3V LVPECL outputs
• Selectable differential CLKxx, nCLKxx inputs
the CLKxx input pairs will be passed to the output. When
COM_SEL is logic Low, the output is determined by the setting
of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1.
• CLKxx, nCLKxx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency: 900MHz (typical)
The differential input has a common mode range that can accept
most differential input types such as LVPECL, LVDS, LVHSTL,
SSTL, and HCSL. The ICS85356I can therefore be used as a
differential translator to translate almost any differential input type
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKxx input
• Output skew: 75ps (typical)
to LVPECL. It can also be used in ECL mode by setting V =0V
CC
• Propagation delay: 1.15ns (typical)
and VEE to -3.0V to - 3.8V.
• LVPECL mode operating voltage supply range:
The ICS85356I adds negligible jitter to the input clock and can
operate at high frequencies in excess of 900MHz thus making
it ideal for use in demanding applications such as SONET,
Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
VCC = 3V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3V to -3.8V
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Compatible with MC100LVEL56
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
VCC
Q0
nQ0
SEL0
COM_SEL
SEL1
VCC
Q1
nQ1
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
VCC
Q0
nQ0
SEL0
COM_SEL
SEL1
VCC
Q1
nQ1
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
CLK0A
nCLK0A
0
Q0
nQ0
CLK0B
1
nCLK0B
SEL0
COM_SEL
SEL1
CLK1B
nCLK1B
9
10
CLK1B
nCLK1B
9
10
VEE
VEE
ICS85356I
20-LeadTSSOP
6.5mm x 4.4mm x 0.92mm
G Package
ICS85356I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm
M Package
CLK1A
nCLK1A
0
Q1
nQ1
CLK1B
1
Top View
Top View
nCLK1B
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REV. A OCTOBER 7, 2004
1
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
VCC
Type
Description
Core supply pin.
Pulldown Non-inverting differential clock input.
14, 20
Power
Input
1
2
CLK0A
nCLK0A
nc
Input
Pullup
Inverting differential clock input.
No connect.
3, 8
4
Unused
Input
CLK0B
nCLK0B
CLK1A
nCLK1A
CLK1B
nCLK1B
VEE
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
5
Input
6
Input
7
Input
9
Input
10
11
12, 13
15
16
17
18, 19
Input
Pullup
Inverting differential clock input.
Power
Output
Input
Negative supply pins.
nQ1, Q1
SEL1
Differential output pairs. LVPECL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
Pullup
COM_SEL
SEL0
Input
Pulldown Common select input. LVCMOS / LVTTL interface levels.
Input
Pullup
Clock select input. LVCMOS / LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
nQ0, Q0
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
KΩ
RPULLDOWN Input Pulldown Resistor
KΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
COM_SEL
SEL1
SEL0
Q0
nQ0
Q1
nQ1
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
CLK0A
CLK0B
CLK0A
CLK0B
CLK0B
nCLK0A
nCLK0B
nCLK0A
nCLK0B
nCLK0B
CLK1A
CLK1A
CLK1B
CLK1B
CLK1B
nCLK1A
nCLK1A
nCLK1B
nCLK1B
nCLK1B
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REV. A OCTOBER 7, 2004
2
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
46.2°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.0
3.3
3.6
40
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage SEL0, SEL1, COM_SEL
2
VCC + 0.3
V
Input Low Voltage SEL0, SEL1, COM_SEL
-0.3
0.8
5
V
SEL0, SEL1
Input High Current
V
CC = VIN = 3.6V
µA
µA
µA
µA
IIH
COM_SEL
VCC = VIN = 3.6V
VCC = 3.6V, VIN = 0V
VCC = 3.6V, VIN = 0V
150
SEL0, SEL1
Input Low Current
-150
-5
IIL
COM_SEL
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0A, CLK0B,
CLK1A, CLK1B
VCC = VIN = 3.6V
150
5
µA
µA
IIH
Input High Current
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
VCC = VIN = 3.6V
CLK0A, CLK0B,
CLK1A, CLK1B
nCLK0A, nCLK0B,
nCLK1A, nCLK1B
V
CC = 3.6V, VIN = 0V
-5
µA
µA
IIL
Input Low Current
VCC = 3.6V, VIN = 0V
-150
VPP
Peak-to-Peak Voltage
0.15
1.0
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V.
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
VSWING
IJ 700MHz
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
900
Maximum Units
MHz
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Rise Time
IJ 900MHz
0.85
1.15
75
1.45
150
580
580
100
ns
ps
ps
ps
ps
tsk(o)
tR
20% to 80%
20% to 80%
200
200
tF
Output Fall Time
todc
Duty Cycle Skew
All parameters measured at IJ 622MHz unless noted otherwise.
This part does not add measurable jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nCLKxA,
nCLKxB
LVPECL
VPP
VCMR
Cross Points
nQx
CLKxA,
CLKxB
VEE
-1.3V 0.165V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nCLKxA,
nCLKxB
CLKxA,
CLKxB
nQ0, nQ1
nQy
Q0, Q1
Qy
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
nQ0, nQ1
Q0, Q1
80%
tF
80%
VSWING
20%
Pulse Width
Clock
20%
tPERIOD
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A OCTOBER 7, 2004
5
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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REV. A OCTOBER 7, 2004
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2:1, DIFFERENTIAL-TO-3.3V
D
UAL LVPECL / ECL CLOCK
MULTIPLEXER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85356I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85356I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 40mA = 144mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.6V, with all outputs switching) = 144mW + 60.4mW = 204.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W perTable 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.204W * 39.7°C/W = 93.1°C. This is well below the limit of 125°C
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6A. Thermal Resistance θJA for 20-pin SOIC, Forced Convection
θJA byVelocity (Linear Feet per Minute)
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
Table 6B. Thermal Resistance θJA for 20-pin TSSOP, Forced Convection
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL = 50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage
ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V – (V - 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 20 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
65.7°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85356I is: 446
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS - 013, MO - 119
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REV. A OCTOBER 7, 2004
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ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
12
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS85356AMI
Marking
Package
Count
38 per tube
1000
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS85356AMI
ICS85356AMI
ICS85356AGI
ICS85356AGI
ICS85356AGIL
20 lead SOIC
ICS85356AMIT
ICS85356AGI
20 lead SOIC on Tape and Reel
20 lead TSSOP
72 per tube
2500
ICS85356AGIT
ICS85356AGILF
20 lead TSSOP on Tape and Reel
20 lead "Lead Free" TSSOP
72 per tube
20 lead "Lead Free" TSSOP on Tape
and Reel
ICS85356AGILFT
ICS85356AGIL
2500
-40°C to 85°C
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
13
ICS85356I
2:1, DIFFERENTIAL-TO-3.3V
DUAL LVPECL / ECL CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
7
13
Added Differential Clock Input Interface section.
Ordering Information Table - added Lead Free part number.
Updated data sheet format.
A
10/7/04
85356AMI
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 7, 2004
14
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