ICS8535AG-21 [ICSI]
LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER; 低偏移， 1到2 LVCMOS / LVTTL - TO- 3.3V的LVPECL扇出缓冲器
| 型号： | ICS8535AG-21 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER |
| 文件： | 总14页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8535-21 is a low skew, high performance • 2 differential 3.3V LVPECL outputs
ICS
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
• Selectable CLK0 or CLK1 inputs for redundant
buffer and a member of the HiPerClockS™fam-
and multiple frequency fanout applications
HiPerClockS™
ily of High Performance Clock Solutions from
ICS.The ICS8535-21 has two single-ended clock
• CLK0 or CLK1 can accept the following input levels:
inputs. The single-ended clock input accepts LVCMOS or
LVTTL input levels and translate them to 3.3V LVPECL lev-
els. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous asser-
tion/deassertion of the clock enable pin.
LVCMOS or LVTTL
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
Guaranteed output and part-to-part skew characteristics
make the ICS8535-21 ideal for those applications demand-
ing well defined performance and repeatability.
• Output skew: 20ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 1.6ns (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
D
CLK_EN
Q
1
2
3
4
5
6
7
VEE
CLK_EN
CLK_SEL
CLK0
14
13
12
11
10
9
VCC
Q0
nQ0
nc
Q1
nQ1
VCC
LE
CLK0
CLK1
0
1
Q0
nQ0
VEE
CLK1
VCC
Q1
nQ1
8
CLK_SEL
ICS8535-21
14-LeadTSSOP
4.4mm x 5.0mm x 0.92mm body package
G Package
Top View
8535AG-21
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REV. A OCTOBER 20, 2004
1
ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 5
VEE
Power
Input
Negative supply pins.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
6
CLK0
CLK1
VCC
Input
Input
Pulldown LVCMOS / LVTTL clock input.
Pulldown LVCMOS / LVTTL clock input.
Positive supply pins.
7, 8, 14
9, 10
11
Power
Output
Unused
Output
nQ1, Q1
nc
Differential output pair. LVPECL interface levels.
No connect.
12, 13
nQ0, Q0
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
KΩ
KΩ
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
CLK0
Q0, Q1
Disabled; LOW
Disabled; LOW
Enabled
nQ0, nQ1
Disabled; HIGH
Disabled; HIGH
Enabled
0
0
1
1
0
1
0
1
CLK1
CLK0
CLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as show in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Enabled
Disabled
CLK0, CLK1
CLK_EN
nQ0, nQ1
Q0, Q1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
CLK0 or CLK1
Q0, Q1
LOW
nQ0, nQ1
HIGH
0
1
HIGH
LOW
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 93.2°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CLK0, CLK1
2
V
CC + 0.3
V
V
VIH
VIL
IIH
Input High Voltage
CLK_EN, CLK_SEL
CLK0, CLK1
2
VCC + 0.3
-0.3
-0.3
1.3
0.8
150
5
V
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL
CLK0, CLK1, CLK_SEL
CLK_EN
V
V
IN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
IN = 0V, VCC = 3.465V
µA
µA
µA
µA
CLK0, CLK1, CLK_SEL
CLK_EN
V
V
-5
IIL
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical
Maximum
266
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
IJ 266MHz
1.0
1.6
tsk(o)
tsk(pp)
20
ps
Part-to-Part Skew; NOTE 3, 5
300
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 4
156.25MHz @ Integration
Range: 12KHz - 20MHz
tjit
0.03
ps
tR/tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ @ 50MHz
300
45
600
55
ps
ꢀ
IJ 200MHz
All parameters measured at IJ 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
ADDITIVE PHASE JITTER
in the 1Hz band to the power in the fundamental. When the
required offset is specified, the phase noise is called a dBc
value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired ap-
plication over the entire time record of the signal. It is math-
ematically possible to calculate an expected bit error rate given
a phase noise plot.
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power
0
-10
-20
-30
-40
Input/Output Additive Phase Jitter,
Integration Range: 12KHz - 20MHz at
156.25MHz = 0.03ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
140
-
-150
160
-
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements device meets the noise floor of what is shown, but can actually
have issues.The primary issue relates to the limitations of the be lower. The phase noise is dependant on the input source
equipment. Often the noise floor of the equipment is higher and measurement equipment.
than the noise floor of the device.This is illustrated above.The
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
PART 1
SCOPE
Qx
nQx
VCC
Qx
LVPECL
VEE
PART 2
nQy
nQx
Qy
tsk(pp)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
nQx
Qx
80ꢀ
tF
80ꢀ
VSWING
Clock
Outputs
20ꢀ
20ꢀ
nQy
tR
Qy
tsk(o)
OUTPUT RISE/FALL TIME
OUTPUT SKEW
nQ0, nQ1
Q0, Q1
CLK0,
CLK1
Pulse Width
tPERIOD
nQ0, nQ1
Q0, Q1
tPW
tPD
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8535-21. The power pin. For ICS8535-21, the unused clock outputs can be
decoupling capacitors should be physically located near the left floating.
Zo = 50
+
Zo = 50
-
VCC = 3.3V
R2
50
R1
50
R3
50
U2
1
14
13
12
11
10
9
VEE
VCC
Q0
nQ0
nc
Q1
nQ1
VCC
CLK_EN
CLK_SEL
CLK0
2
3
4
5
6
7
CLK_EN
CLK_SEL
CLK0
VEE
CLK1
VCC
CLK1
8
8535-21
Vcco = 3.3V
R4
133
R6
133
(U1-7)
(U1-8)
(U1-14)
VCC
Zo = 50
Zo = 50
+
-
C1
10uf
C2
.1uF
C3
.1uF
C4
.1uF
R5
82.5
R7
82.5
Optional Termination
FIGURE 3. ICS8535-21 LVPECL BUFFER SCHEMATIC EXAMPLE
8535AG-21
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 50mA = 173.25mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 x 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 60mW = 233.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 85.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.233W * 85.5°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 14-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
125.2°C/W
85.5°C/W
500
112.1°C/W
81.2°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
146.4°C/W
93.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8535AG-21
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A OCTOBER 20, 2004
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ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 14 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
200
125.2°C/W
85.5°C/W
500
112.1°C/W
81.2°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
146.4°C/W
93.2°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8535-21 is: 412
8535AG-21
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ICS8535-21
Integrated
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LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
PACKAGE OUTLINE - G SUFFIX FOR 14 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
14
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
8535AG-21
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REV. A OCTOBER 20, 2004
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<
ICS8535-21
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT
BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
94 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8535AG-21
ICS8535AG-21T
8535AG21
8535AG21
14 lead TSSOP
14 lead TSSOP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8535AG-21
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REV. A OCTOBER 20, 2004
14
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