ICS854058 [ICSI]
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER; 差分至LVDS时钟多路复用器
| 型号： | ICS854058 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER |
| 文件： | 总12页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS854058 is an 8:1 Differential-to-LVDS Clock • High speed 8:1 differential multiplexer
ICS
Multiplexer which can operate up to 2.5GHz and
• 1 differential LVDS output
HiPerClockS™
is a member of the HiPerClockS™family of High
Performance Clock Solutions from ICS. The
ICS854058 has 8 selectable differential clock in-
• 8 selectable differential PCLK, nPCLK inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
puts.The PCLK, nPCLK input pairs can accept LVPECL, LVDS,
CML or SSTL levels.The fully differential architecture and low
propagation delay make it ideal for use in clock distribution cir-
cuits.The select pins have internal pulldown resistors.The SEL2
pin is the most significant bit and the binary number applied to
the select pins will select the same numbered data input (i.e.,
000 selects PCLK0, nPCLK0).
• Maximum output frequency: 2.5GHz
• Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
• Part-to-part skew: TBD
• Propagation delay: 595ps (typical)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
24
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK7
23 nPCLK7
22 PLCK6
21 nPCLK6
PCLK0
000
nPCLK0
20
19
18
17
16
15
14
13
VDD
Q0
nQ0
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
PCLK1
001
nPCLK1
PCLK2
010
9
nPCLK2
10
11
12
PCLK3
011
nPCLK3
Q0
nQ0
PCLK4
100
ICS854058
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
nPCLK4
PCLK5
101
nPCLK5
Top View
PCLK6
110
nPCLK6
PCLK7
111
nPCLK7
SEL0
SEL1
SEL2
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
854058AG
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REV. A APRIL 8, 2004
1
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
1
PCLK0
Input
Input
Input
Input
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
2
3
4
nPCLK0
PCLK1
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
nPCLK1
Pullup/Pulldown
5, 20
6, 7, 8
9
VDD
Power
Input
Input
Positive supply pins.
SEL0, SEL1, SEL2
PCLK2
Pulldown
Pulldown
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
10
11
12
nPCLK2
PCLK3
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
nPCLK3
Pullup/Pulldown
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
13
14
15
nPCLK4
PCLK4
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
nPCLK5
Pullup/Pulldown
Pulldown
16
17
PCLK5
GND
Input
Power
Output
Non-inverting differential LVPECL clock input.
Power supply ground.
18, 19
nQ0, Q0
Differential output pair. LVDS interface levels.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
21
22
23
24
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
VDD/2 default when left floating.
Pullup/Pulldown
Pulldown
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
854058AG
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REV. A APRIL 8, 2004
2
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistor
75
50
KΩ
KΩ
RVDD/2
Pullup/Pulldown Resistors
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
SEL2
SEL1
SEL0
Q0
nQ0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
854058AG
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REV. A APRIL 8, 2004
3
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO
Continuous Current
10mA
15mA
Surge Current
PackageThermal Impedance, θ
70°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ
Symbol Parameter Test Conditions
Minimum
Typical
3.3
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.465
V
68
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage SEL0:SEL2
2
VDD + 0.3
0.8
V
V
Input Low Voltage SEL0:SEL2
Input High Current SEL0:SEL2
Input Low Current SEL0:SEL2
-0.3
VDD = VIN = 3.465V
150
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-10
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ
Symbol Parameter Test Conditions
DD = VIN = 3.465V
Minimum
Typical Maximum Units
PCLK0:PCLK7
nPCLK0:nPCLK7
PCLK0:PCLK7
nPCLK0:nPCLK7
V
150
150
µA
µA
µA
µA
V
IIH
Input High Current
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
-10
-150
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.15
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.2
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VDD + 0.3V.
854058AG
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REV. A APRIL 8, 2004
4
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOD
Differential Output Voltage
350
50
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.25
50
∆ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = 3.135V TO 3.465V
Symbol Parameter Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
2.5
GHz
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
595
TBD
180
tsk(pp)
tR / tF
ps
20ꢀ to 80ꢀ
ps
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
854058AG
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REV. A APRIL 8, 2004
5
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
Qx
nPCLK0:7
3.3V 5ꢀ
Power Supply
Float GND
VPP
VCMR
Cross Points
LVDS
+
-
PCLK0:7
GND
nQx
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK0:7
PCLK0:7
nQ0
nQx
PART 1
Qx
nQy
PART 2
Qy
Q0
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
VDD
out
out
80ꢀ
tF
80ꢀ
VOD
➤
DC Input
LVDS
Clock
20ꢀ
20ꢀ
Outputs
tR
VOS/∆ VOS
➤
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE
VDD
➤
out
LVDS
DC Input
100
V
OD/∆ VOD
➤
out
DIFFERENTIAL OUTPUT VOLTAGE
854058AG
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REV. A APRIL 8, 2004
6
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD= 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω differ- put. For a multiple LVDS outputs buffer, if only partial outputs
ential transmission line environment, LVDS drivers require a are used, it is recommended to terminate the un-used outputs.
matched load termination of 100Ω across near the receiver in-
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
854058AG
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REV. A APRIL 8, 2004
7
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
LVPE CL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 3A to 3E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL IN DRIVER
BY A CML DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
854058AG
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REV. A APRIL 8, 2004
8
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
SCHEMATIC EXAMPLE
An application schematic example of ICS854058 is shown
in Figure 4. The inputs can accept various types of differential
near the receivers. It is recommended at least one
decoupling capacitor per power pin. The decoupling ca-
signals. In this example, the inputs are driven by LVDS drivers. pacitor should be low ESR and located as close as pos-
sible to the power pin.
The transmission lines are assumed to be 100Ω differential.
The 100Ω matched loads termination should be located
Logic Control Input Examples
Zo = 50
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
R1
100
Zo = 50
RU1
1K
RU2
Not Install
LVDS
100 Ohm Differential
100 OhmDifferential
To Logic
Input
pins
To Logic
Input
pins
RD1
RD2
1K
Not Install
Zo = 50
U1
R2
100
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
PCLK7
nPCLK7
PCLK6
nPCLK6
VDD
Zo = 50
Zo = 50
3.3V
3.3V
+
LVDS
R3
100
SEL0
Q0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nQ0
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
C1
0.1u
Zo = 50
-
LVDS
C2
0.1u
100 Ohm Differential
ICS854058
FIGURE 4. ICS854058 SCHEMATIC EXAMPLE
854058AG
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REV. A APRIL 8, 2004
9
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
TRANSISTOR COUNT
The transistor count for ICS854058 is: 361
854058AG
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REV. A APRIL 8, 2004
10
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
854058AG
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REV. A APRIL 8, 2004
11
PRELIMINARY
ICS854058
Integrated
Circuit
Systems, Inc.
8:1
D
IFFERENTIAL
-
TO-LVDS CLOCK
MULTIPLEXER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
-40°C to 85°C
-40°C to 85°C
ICS854058AG
ICS854058AG
ICS854058AG
ICS854058AG
24 Lead TSSOP
24 Lead TSSOP on Tape and Reel
60 per tube
2500
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
854058AG
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REV. A APRIL 8, 2004
12
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