ICS85408BGLFT [ICSI]
LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP; 低偏移， 1至8差分至LVDS时钟分配芯片
| 型号： | ICS85408BGLFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS85408 is a low skew, high performance • 8 Differential LVDS outputs
ICS
1-to-8 Differential-to-LVDS Clock Distribution
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
HiPerClockS™
Chip and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS.The ICS85408 CLK, nCLK pair can ac-
• Maximum output frequency: 700MHz
cept most differential input levels and translates them to 3.3V
LVDS output levels. Utilizing Low Voltage Differential
Signaling (LVDS), the ICS85408 provides a low power, low
noise, low skew, point-to-point solution for distributing LVDS
clock signals.
• Translates any differential input signal (LVPECL, LVHSTL,
SSTL, HCSL) to LVDS levels without external bias networks
• Translates any single-ended input signal to LVDS with
resistor bias on nCLK input
Guaranteed output and part-to-part skew specifications make
the ICS85408 ideal for those applications demanding well
defined performance and repeatability.
• Multiple output enable inputs for disabling unused outputs
in reduced fanout applications
• Output skew: 50ps (maximum)
• Part-to-part skew: 550ps (maximum)
• Propagation delay: 2.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
PIN ASSIGNMENT
OE
1
2
3
4
24
23
22
21
20
19
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
Q7
nQ7
OE
GND
VDD
VDD
Q0
nQ0
Q1
nQ1
5
6
7
8
Q2
nQ2
18 GND
VDD
CLK
17
16
9
Q3
nQ3
10
11
12
15 nCLK
14
13
CLK
nCLK
Q0
nQ0
Q4
nQ4
Q5
nQ5
ICS85408
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Q6
nQ6
Q7
nQ7
Top View
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
1
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
nQ6, Q6
Output
Differential output pair. LVDS interface levels.
3, 4
5, 6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
Output
Output
Output
Output
Output
Output
Input
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
7, 8
9, 10
11, 12
13, 14
15
Pullup
16
CLK
Input
Pulldown Non-inverting differential clock input.
Positive supply pins.
17, 19, 20
18, 21
VDD
Power
Power
GND
Power supply ground.
Output enable. Controls the enabling and disabling of outputs
22
OE
Input
Pullup
Qx, nQx. When HIGH, the outputs are enabled. When LOW, the
outputs are in HiZ. LVCMOS / LVTTL interface levels.
23, 24
nQ7, Q7
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
CPD
4
pF
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
OE
0
Q0:Q7
nQ0:nQ7
HiZ
HiZ
1
ACTIVE
ACTIVE
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0:Q7
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQ0:nQ7
HIGH
LOW
0
1
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
0
Biased; NOTE 1
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
LOW
HIGH
Inverting
NOTE 1: Please refer to the Application Information section "Wiring the Differential Input to Accept Single Ended Levels".
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
2
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
10mA
15mA
Surge Current
PackageThermal Impedance, θ
70°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
90
V
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage OE
2
VDD + 0.3
V
V
Input Low Voltage OE
Input High Current OE
Input Low Current OE
-0.3
0.8
5
VDD = VIN = 3.465V
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Input High Current
Test Conditions
Minimum Typical Maximum Units
CLK
VIN = VDD = 3.465V
150
5
µA
µA
µA
µA
V
IIH
nCLK
CLK
V
IN = VDD = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
nCLK
V
-150
0.15
VPP
Peak-to-Peak Voltage
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined ast VIH.
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
3
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Δ VOD
VOS
Differential Output Voltage
250
400
600
50
mV
mV
V
RL = 100Ω
VOD Magnitude Change
Offset Voltage
1.125
1.4
1.6
50
RL = 100Ω
Δ VOS
IOZ
VOS Magnitude Change
mV
µA
µA
mA
mA
High Impedance Leakage Current
Power Off Leakage
-10
-1
+10
+1
IOFF
IOSD
Differential Output Short Circuit Current
Output Short Circuit Current
-5.5
-12
I
OS/IOSB
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
700
2.4
50
550
600
55
5
MHz
ns
ps
ps
ps
ꢀ
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
1.6
tsk(o)
tsk(pp)
tR / tF
odc
20ꢀ to 80ꢀ
50
45
Output Duty Cycle
t
PZL, tPZH Output Enable Time; NOTE 5
PLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
t
5
All parameters measured at f ≤ 622MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This paragraph is defined according with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production 5.
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
4
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD
3.3V
SCOPE
Qx
nCLK
CLK
Power Supply
Float GND
VPP
VCMR
Cross Points
LVDS
+
-
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
PART 1
Qx
PART 2
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nQ0:nQ7
nCLK
CLK
Q0:Q7
Pulse Width
tPERIOD
nQ0:nQ7
Q0:Q7
tPW
odc =
tPD
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
5
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
VDD
out
80ꢀ
tF
80ꢀ
tR
➤
DC Input
LVDS
VOD
Clock
Outputs
20ꢀ
20ꢀ
out
VOS/Δ VOS
➤
OUTPUT RISE/FALL TIME
VOS SETUP
VDD
VDD
out
out
➤
out
out
IOSD
LVDS
DC Input
DC Input
100
V
OD/Δ VOD
LVDS
➤
VOD SETUP
IOSD SETUP
VDD
out
IOS
DC Input
LVDS
LVDS
VDD
IOSB
IOFF
out
IOS SETUP
IOFF SETUP
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
6
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100Ω differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
3.3V
Zo = 50 Ohm
3.3V
LVDS_DRIVER
CLK
R1
100
nCLK
HiPerClockS
Zo = 50 Ohm
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
7
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
8
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS85408 is: 1821
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
9
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-153
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
10
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS85408BG
ICS85408BGT
ICS85408BGLF
ICS85408BGLFT
ICS85408BG
ICS85408BG
TBD
24 Lead TSSOP
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
24 Lead TSSOP
1000 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
TBD
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
11
ICS85408
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T6
9
Reliability Table - revised air flow from Linear Feet per Minute to Meters per
Second.
A
5/6/04
T8
11
Ordering Information Table - corrected typo in Part/Order Number from
ICS8540BG to ICS85408BG.
A
A
1
Pin Assignment - corrected package information from 300-MIL to 173-MIL
8/25/04
4/25/05
1
11
Features Section - added Lead-Free bullet. Corrected Block Diagram.
Ordering Information Table - Added Lead-Free part number.
T8
85408BG
www.icst.com/products/hiperclocks.html
REV. A APRIL 25, 2005
12
相关型号：
ICS854104AG
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
IDT
ICS854104AGLF
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS854104AGLFT
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS854104AGT
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
IDT
ICS854105AG
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
IDT
ICS854105AGLF
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS854105AGLFT
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS854105AGT
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
IDT
©2020 ICPDF网 联系我们和版权申明