ICS854105AGT [IDT]
Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16;
| 型号： | ICS854105AGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 854104 Series, 4 True Output(s), 4 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总11页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LOW SKEW, 1-4 LVCMOS/LVTTL-TO-
LVDS FANOUT BUFFER
ICS854105
GENERAL DESCRIPTION
FEATURES
The ICS854105 is a low skew, high performance 1-
• Four LVDS outputs
ICS
HiPerClockS™
to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer
and a member of the HiPerClockS™ family of High
• One single-ended LVCMOS/LVTTL clock input
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Translates single-ended input signals to LVDS levels
• Additive phase jitter, RMS: 0.15ps (typical)
• Output skew: TBD
Performance Clock Solutions from IDT. Utilizing
Low Voltage Differential Signaling (LVDS), the
ICS854105 provides a low power, low noise, solution for dis-
tributing clock signals over controlled impedances of 100Ω.
The ICS854105 accepts an LVCMOS/LVTTL input level and
translates it to LVDS output levels.
Guaranteed output and part-to-part skew characteristics make
the ICS854105 ideal for those applications demanding well
defined performance and repeatability.
• Part-to-part skew: TBD
• Propagation delay: 1.3ns (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
1
2
3
4
5
6
7
8
OE0
OE1
OE2
VDD
GND
CLK
nc
16
15
14
13
12
11
10
9
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ0
Pullup
OE0
Q1
nQ1
OE1
OE3
nQ3
Pullup
Pullup
Pulldown
CLK
ICS854105
16-Lead TSSOP
Q2
nQ2
OE2
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
Q3
nQ3
OE3
Pullup
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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ICS854105AG REV. A JANUARY 18, 2007
ICS854105
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Output enable pin for Q0, nQ0 output. If OE pin is LOW, outputs will
drive HiZ. LVCMOS/LVTTL interface levels.
Output enable pin for Q1, nQ1 outputs. If OE pin is LOW, outputs
will drive HiZ. LVCMOS/LVTTL interface levels.
Output enable pin for Q2, nQ2 outputs. If OE pin is LOW, outputs
will drive HiZ. LVCMOS/LVTTL interface levels.
1
OE0
Input
Input
Input
Pullup
Pullup
Pullup
2
3
OE1
OE2
4
5
6
7
VDD
GND
CLK
nc
Power
Power
Input
Positive supply pin.
Power supply ground.
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Unused
Output enable pin for Q3, nQ3 outputs. If OE pin is LOW, outputs
will drive HiZ. LVCMOS/LVTTL interface levels.
8
OE3
Input
Pullup
9, 10
11, 12
13, 14
15, 16
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
TABLE 3. OE[3:0] FUNCTION TABLE
Inputs
Outputs
Q0/nQ0:Q3/nQ3
HiZ (default)
Active
OE[3:0]
0
1
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage% VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs% V
-0.±V to VDD + 0.±V
I
Outputs% IO
Continuous Current
Surge Current
10mA
1±mA
Package Thermal Impedance% θ 93.3°C/W (0 lfpm)
JA
Storage Temperature% T
-6±°C to 1±0°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±±5% TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.13±
3.3
60
3.46±
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±±5% TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
Input Low Voltage
-0.3
0.8
1±0
±
V
CLK
VDD = VIN = 3.46±V
VDD = VIN = 3.46±V
DD = 3.46±V% VIN = 0V
µA
µA
µA
IIH
Input High Current
OE[0:3]
CLK
V
-±
IIL
Input Low Current
OE[0:3]
VDD = 3.46±V% VIN = 0V
-1±0
µA
NOTE: Outputs terminated with ±0Ω to VDD/2. See Parameter Measurement Information% "Output Load Test Circuit".
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V±±5% TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOD
Differential Output Voltage
3±0
30
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.3
20
Δ VOS
VOS Magnitude Change
mV
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
(12kHz to 20MHz)
20ꢀ to 80ꢀ
Minimum Typical Maximum Units
250
MHz
ns
Propagation Delay; NOTE 1
1.3
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
0.15
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
TBD
TBD
400
50
ps
ps
ps
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2 of the input to the differential output crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at
the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
3.3V
nQx
Qx
SCOPE
Qx
3.3V 5ꢀ
POWER SUPPLY
+
Float GND –
LVDS
nQy
Qy
nQx
tsk(o)
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQx
PART 1
Qx
CLK
nQ0:nQ3
Q0:Q3
nQy
PART 2
Qy
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
nQ0:nQ3
80ꢀ
80ꢀ
tR
Q0:Q3
VOD
tPW
Clock
20ꢀ
20ꢀ
tPERIOD
Outputs
tF
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
VDD
VDD
out
out
➤
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
VOS/Δ VOS
➤
out
➤
OFFSET VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 1. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100Ω DifferentialTransmission Line
FIGURE 1. TYPICAL LVDS DRIVER TERMINATION
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS854105.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854105 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
•
Power_ = V
* I
= 3.465V * 60mA = 207.9mW
DD_MAX
MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming air flow
of 200 linear feet per minute and a multi-layer board, the appropriate value is 88.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.208W * 88.9°C/W = 88.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 16-PIN TSSOP, FORCED CONVECTION
JA
θ vs. 0 Air Flow (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
93.3°C/W
88.9°C/W
86.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
93.3°C/W
88.9°C/W
86.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854105 is: 286
Pin compatible with SN65LVDS105
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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ICS854105AG REV. A JANUARY 18, 2007
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS854105AG
Marking
854105AG
854105AG
TBD
Package
Shipping Packaging Temperature
16 Lead TSSOP
16 Lead TSSOP
16 Lead TSSOP
16 Lead TSSOP
tube
0°C to 70°C
ICS854105AGT
ICS854105AGLF
ICS854105AGLFT
2500 tape & reel
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ 1-TO-4 LVDS FANOUT BUFFER
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ICS854105AG REV. A JANUARY 18, 2007
ICS854105
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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