ICS86953BYI-147 [ICSI]
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER; 差分至LVCMOS / LVTTL零延迟缓冲器
| 型号： | ICS86953BYI-147 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER |
| 文件： | 总13页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS86953I-147 is a low voltage, low skew • 9 single ended LVCMOS/LVTTL outputs;
ICS
1-to-9 Differential-to-LVCMOS/LVTTL Clock
Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS.The PCLK, nPCLK pair can accept most stan-
(8) clocks, (1) feedback
HiPerClockS™
• PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
dard differential input levels.With output frequencies up to 175MHz,
the ICS86953I-147 is targeted for high performance clock ap-
plications. Along with a fully integrated PLL, the ICS86953I-147
contains frequency configurable outputs and an external feed-
back input for regenerating clocks with “zero delay”.
• Maximum output frequency: PLL Mode, 175MHz
• VCO range: 250MHz to 700MHz
• Output skew: 75ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• Static phase offset: 90ps 110ps
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC953
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
VDDA
FB_CLK
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q1
VDDO
Q2
nc
GND
Q3
ICS86953I-147
nc
nc
VDDO
Q4
GND
PCLK
GND
9
10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
BLOCK DIAGRAM
QFB
PCLK
nPCLK
0
1
0
1
7
Q0:Q6
Q7
/
0
1
Phase
Detector
÷4
LPF
VCO
FB_CLK
÷2
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
86953BYI-147
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REV. B APRIL 23, 2004
1
ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDA
Type
Description
1
2
Power
Input
Analog supply pin.
FB_CLK
nc
Pullup
Feedback clock input. LVCMOS / LVTTL interface levels.
No connect.
3, 4, 5, 6
Unused
7, 13, 17,
21, 25, 29
GND
PCLK
nPCLK
Power
Input
Input
Power supply ground.
8
Pullup
Non-inverting LVPECL differential clock input.
Pullup/ Inverting LVPECL differential clock input.
Pulldown Internally biased to VDDO/2.
9
Active HIGH Master Reset. Active LOW output enable. When
logic High, the internal dividers are reset and the outputs are
tri-stated (HiZ). When logic LOW, the internal dividers and
the outputs are enabled. LVCMOS / LVTTL interface levels.
10
MR/nOE
VDDO
Input
Pulldown
11, 15, 19, 23, 27
Power
Output
Output supply pins.
12, 14, 16, 18,
20, 22, 24, 26
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Clock outputs. LVCMOS / LVTTL interface levels.
14Ω typical output impedance.
Feedback clock output. LVCMOS / LVTTL interface levels.
14Ω typical output impedance.
28
QFB
Output
Selects VCO when HIGH. When LOW, selects PCLK,
nPCLK. LVCMOS / LVTTL interface levels.
30
31
32
PLL_SEL
nBYPASS
VCO_SEL
Input
Input
Input
Pullup
Pullup
Pullup
Selects PLL when HIGH. When LOW, in Bypass mode.
Selects VCO ÷2 when HIGH. Selects VCO ÷1 when LOW.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
Ω
RPULLUP
51
51
7
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance (per output)
Output Impedance
VDDA, VDDO = 3.465V
5
12
ROUT
14
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Input
Outputs
QFB, Q0:Q7
HiZ
MR/nOE
1
0
Enabled
TABLE 3B. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs
Outputs
QFB, Q0:Q7
CLK
Operation
Bypass
PLL_SEL VCO_SEL
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Test Mode: PLL and divider bypass
Test Mode: PLL bypass
Test Mode: PLL bypass
PLL Mode
CLK/4
CLK/8
VCO/4
PLL Mode
VCO/8
86953BYI-147
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDDA
VDDO
IDDA
Analog Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
20
V
Output Supply Voltage
Analog Supply Current
Output Supply Current
V
mA
mA
IDDO
75
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, nBYPASS,
PLL_SEL, MR/nOE
2
VDD + 0.3
V
V
V
Input
VIH
High Voltage
FB_CLK
2
VDD + 0.3
VCO_SEL, nBYPASS,
PLL_SEL, MR/nOE
-0.3
-0.3
0.8
Input
VIL
Low Voltage
FB_CLK
1.3
V
µA
V
IIN
Input Current
120
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
IOH = -20mA
IOL = 20mA
VDD - 0.6
0.6
V
NOTE: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load Test Circuit".
TABLE 4C. LVPECL DC CHARACTERISTICS, VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
IIN
Input Current
120
1.3
µA
V
VPP
VCMR
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
0.15
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
86953BYI-147
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fREF Input Reference Frequency 175 MHz
TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VCO_SEL = 1
VCO_SEL = 0
Minimum Typical Maximum Units
PLL Mode
31.25
62.50
87.5
175
200
MHz
MHz
MHz
fMAX
Output Frequency
PLL Mode
Bypass Mode
Propagation Delay;
NOTE 1
tPD
PCLK, nPCLK
2.5
4
ns
ps
Measured on rising edge
at VDD/2
tsk(o)
Output Skew; NOTE 2, 4
75
tjitter(cc) Cycle-to-Cycle Jitter; NOTE 5
50
200
700
53
10
6
ps
ps
ps
ꢀ
t(Ø)
tR / tF
odc
tLOCK
tEN
Static Phase Offset; NOTE 3, 5
Output Rise/Fall Time
-20
100
47
90
50
20ꢀ to 80ꢀ
Output Duty Cycle
PLL Lock Time
ms
ns
ns
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
tDIS
7
NOTE: Termination of 50Ω to VDD/2.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
VDD
SCOPE
VDDA
VDDO
,
nPCLK
Qx
VPP
VCMR
Cross Points
LVCMOS
GND
PCLK
GND
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDDO
2
VDDO
VDDO
2
VDDO
2
Q0:Q7,
QFB
Qx
2
➤
➤
tcycle n
tcycle n+1
➤
➤
VDDO
2
Qy
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nPCLK
PCLK
80ꢀ
tF
80ꢀ
20ꢀ
20ꢀ
Clock
Outputs
VDDO
2
tR
Q0:Q7,
QFB
t
PD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nPCLK
PCLK
VOH
VOL
VDDO
2
Q0:Q7
QFB
Pulse Width
VOH
tPERIOD
VDDO
VO2L
FB_CLK
➤
t(Ø)
➤
tPW
odc =
tPERIOD
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PHASE JITTER & STATIC PHASE OFFSET
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS86953I-147 provides sepa-
rate power supplies to isolate any high switching noise from the
outputs to the internal PLL.VDDA and VDDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 2
illustrates how a 10Ω resistor along with a 10µF and a .01µF
bypass capacitor should be connected to each VDDA pin.
3.3V
VDDO
.01µF
.01µF
10Ω
VDDA
10 µF
FIGURE 2. POWER SUPPLY FILTERING
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Integrated
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Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
PCLK/nPCLK CLOCK INPUT INTERFACE
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 3A to 3D show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL IN DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
LAYOUT GUIDELINE
The schematic of the ICS86953I-147 layout example is shown in depend on the selected component types, the density of the
Figure 4A.The ICS86953I-147 recommended PCB board layout components, the density of the traces, and the stack up of the
for this example is shown in Figure 4B. This layout example is P.C.board.
used as a general guideline.The layout in the actual system will
VDD
R10
1K
R8
1K
R9
1K
R1
36
Zo = 50
VDD
U1
R7
10 - 15
24
23
22
21
20
19
18
17
1
VDDA
Q1
VDDO
Q2
GND
Q3
VDDO
Q4
GND
2
3
4
5
6
7
8
FB_CLK
nc
nc
nc
nc
GND
PCLK
C16
10u
C11
0.01u
VCC
Zo = 50 Ohm
Zo = 50 Ohm
ICS86953I-147
VDD
LVPECL Driv er
Zo = 50
R3
50
R4
50
R6
1K
R2
36
C6 (Option)
0.1u
R5
50
(U1-15)
(U1-11)
(U1-19) (U1-23)
(U1-27)
VDD
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C1
0.1uF
F
IGURE 4A. ICS86953I-147 LVCMOS ZERO
D
ELAY
B
UFFER
SCHEMATIC
E
XAMPLE
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
P
OWER AND
G
ROUNDING
• The 50Ω output traces should have same length.
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred.This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
• Avoid sharp angles on the clock trace.Sharp angle turns
cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
C
LOCK
T
RACES AND
TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
GND
50 Ohm
Trace
VDD
R1
C1
R7
VCCA
C16
VIA
Other
signals
U1
Pin 1
C11
C5
C4
R2
C2
C3
50 Ohm
Trace
FIGURE 4B. PCB BOARD LAYOUT FOR ICS86953I-147
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REV. B APRIL 23, 2004
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ICS86953I-147
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86953I-147 is: 1758
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Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS86953I-147
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Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS86953BYI-147
ICS86953BYIT-147
ICS6953BI147
ICS6953BI147
32 Lead LQFP
32 Lead LQFP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. B APRIL 23, 2004
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Systems, Inc.
LOW
SKEW, 1-TO-9
D
IFFERENTIAL
-
TO-LVCMOS / LVTTL ZERO
DELAY
BUFFER
REVISION HISTORY SHEET
Description of Change
Added Pullup/Pulldown to Pin 9.
Pin Characteristics table - changed CIN limit from 4pF max. to 4pF typical.
Added 5pF min. and 7pF typical to CPD.
Updated Figure 3C and 3D.
Added Layout Guideline and PCB Board layout.
Pin Characteristics Table - added ROUT row.
Rev
B
Table
T1
T2
Page
2
2
Date
10/28/03
4/23/04
7
8 & 9
2
T2
B
86953BYI-147
www.icst.com/products/hiperclocks.html
REV. B APRIL 23, 2004
13
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