ICS87004AGT [ICSI]
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR; 1 ： 4 ，差分至LVCMOS / LVTTL零延迟时钟发生器
| 型号： | ICS87004AGT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR |
| 文件： | 总14页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87004 is a highly versatile 1:4 Differential- • 4 LVCMOS/LVTTL outputs, 7Ω typical output impedance
ICS
to-LVCMOS/LVTTL Clock Generator and a mem-
• Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
ber of the HiPerClockS™family of High Perfor-
HiPerClockS™
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
mance Clock Solutions from ICS. The ICS87004
has two selectable clock inputs.The CLK0, nCLK0
and CLK1, nCLK1 pairs can accept most standard differential
input levels. Internal bias on the nCLK0 and nCLK1 inputs
allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL.
The ICS87004 has a fully integrated PLL and can be configured
as zero delay buffer, multiplier or divider and has an input and
output frequency range of 15.625MHz to 250MHz. The refer-
ence divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios:8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.The exter-
nal feedback allows the device to achieve “zero delay” between
the input clock and the output clocks.The PLL_SEL pin can be
used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
• Internal bias on nCLK0 and nCLK1 to support
LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 45ps (maximum)
• Static phase offset: 50 125ps (ꢀ.ꢀV 5ꢁ)
• Full ꢀ.ꢀV or 2.5V operating supply
• 5V tolerant inputs
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PLL_SEL
PIN ASSIGNMENT
1
2
ꢀ
4
5
6
7
8
24
2ꢀ
22
21
20
19
18
Q1
VDDO
Q2
GND
Q0
VDDo
Q0
Q1
Q2
Qꢀ
÷2, ÷4, ÷8, ÷16,
÷ꢀ2, ÷64, ÷128
0
1
CLK0
nCLK0
SEL0
SEL1
SEL2
SELꢀ
CLK_SEL
VDD
GND
0
1
Qꢀ
VDDO
MR
CLK1
nCLK1
PLL
17
16
15
14
1ꢀ
FB_IN
9
PLL_SEL
CLK1
nCLK1
CLK_SEL
FB_IN
10
11
12
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
CLK0
nCLK0
GND
VDDA
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
G Package
Top View
SEL0
SEL1
SEL2
SELꢀ
MR
87004AG
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REV. A JUNE 16, 2004
1
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Power
Description
1, 12, 21
GND
Power supply ground.
Q0, Qꢀ,
Q2, Q1
Clock outputs. 7Ω typical output impedance.
2, 20, 22, 24
ꢀ, 19, 2ꢀ
Output
LVCMOS/LVTTL interface levels.
VDDO
Power
Output supply pins.
SEL0, SEL1,
SEL2, SELꢀ
Determines output divider values in Table ꢀ.
LVCMOS/LVTTL interface levels.
4, 5, 6, 7
Input Pulldown
Clock select input. When HIGH, selects differential CLK1, nCLK1.
8
CLK_SEL
Input Pulldown When LOW, selects differential CLK0, nCLK0.
LVCMOS/LVTTL interface levels.
9
VDD
Power
Core supply pin.
10
CLK0
Input Pulldown Non-inverting differential clock input.
Pullup/
11
1ꢀ
14
15
nCLK0
VDDA
Input
Power
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Analog supply pin.
Pullup/
Pulldown
nCLK1
CLK1
Inverting differential clock input. VDD/2 default when left floating.
Input Pulldown Non-inverting differential clock input.
Selects between the PLL and reference clock as input to the dividers.
16
17
18
PLL_SEL
FB_IN
MR
Input
Pullup
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL feedback input to phase detector for regenerating
Input Pulldown clocks with "zero delay". Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
Input Pulldown reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
VDD, VDDA, VDDO = ꢀ.465V
VDD, VDDA, VDDO = 2.625V
2ꢀ
17
12
pF
pF
Ω
Power Dissipation Capacitance
(per output)
CPD
ROUT
Output Impedance
5
7
87004AG
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REV. A JUNE 16, 2004
2
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
TABLE 3A. PLL ENABLE FUNCTION TABLE
Outputs
Inputs
SEL0
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)
125 - 250
Q0:Q3
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
62.5 - 125
ꢀ1.25 - 62.5
15.625 -ꢀ1.25
125 - 250
62.5 - 125
ꢀ1.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
ꢀ1.25 - 62.5
15.625 - ꢀ1.25
ꢀ1.25 - 62.5
15.625 - ꢀ1.25
15.625 - ꢀ1.25
x 2
x 2
x 4
x 4
x 8
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0:Q3
÷ 8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 8
÷ 8
÷ 16
÷ 16
÷ 16
÷ ꢀ2
÷ ꢀ2
÷ 64
÷ 128
÷ 4
÷ 4
÷ 8
÷ 2
÷ 4
÷ 2
87004AG
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REV. A JUNE 16, 2004
ꢀ
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = ꢀ.ꢀV 5ꢁ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
ꢀ.1ꢀ5
ꢀ.1ꢀ5
ꢀ.1ꢀ5
ꢀ.ꢀ
ꢀ.ꢀ
ꢀ.ꢀ
ꢀ.465
ꢀ.465
ꢀ.465
100
16
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
6
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = ꢀ.ꢀV 5ꢁ OR 2.5V 5ꢁ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SELꢀ,
FB_IN, MR
PLL_SEL, CLK_SEL,
SEL0, SEL1, SEL2, SELꢀ,
FB_IN, MR
Input
VIH
2
VDD + 0.ꢀ
0.8
V
V
High Voltage
Input
VIL
-0.ꢀ
Low Voltage
V
DD = VIN = ꢀ.465V,
CLK_SEL, MR, FB_IN,
SEL0, SEL1, SEL2, SELꢀ
150
5
µA
µA
µA
µA
V
DD = VIN = 2.625V
Input
IIH
High Current
V
DD = VIN = ꢀ.465V,
PLL_SEL
V
DD = VIN = 2.625V
VDD = ꢀ.465V, VIN = 0V,
VDD = 2.625V, VIN = 0V
CLK_SEL, MR, FB_IN,
SEL0, SEL1, SEL2, SELꢀ
-5
Input
IIL
Low Current
V
DD = ꢀ.465V, VIN = 0V,
PLL_SEL
-150
V
DD = 2.625V, VIN = 0V
VDDO = ꢀ.465V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.625V
VDDO = ꢀ.465V or 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section,
see Output Load Test Circuit Diagrams.
87004AG
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REV. A JUNE 16, 2004
4
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = ꢀ.ꢀV 5ꢁ OR 2.5V 5ꢁ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD = VIN = ꢀ.465V,
VDD = VIN = 2.625V
Minimum Typical Maximum Units
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
150
150
µA
µA
µA
µA
IIH
Input High Current
VDD = VIN = ꢀ.465V,
VDD = VIN = 2.625V
VDD = ꢀ.465V, VIN = 0V,
VDD = 2.625V, VIN = 0V
VDD = ꢀ.465V, VIN = 0V,
VDD = 2.625V, VIN = 0V
-5
IIL
Input Low Current
nCLK0, nCLK1
-150
VPP
Peak-to-Peak Input Voltage
0.15
1.ꢀ
V
V
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
V
DD - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.ꢀV.
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢁ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.ꢀ75
2.ꢀ75
2.ꢀ75
2.5
2.5
2.5
2.625
2.625
2.625
96
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
6
87004AG
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REV. A JUNE 16, 2004
5
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = ꢀ.ꢀV 5ꢁ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
15.625
250
MHz
Propagation Delay,
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V
f ≤ 250MHz, Qx ÷ 2
5
6
ns
Static Phase Offset; CLK0, nCLK0
PLL_SEL = ꢀ.ꢀV
fREF ≤ 167MHz, Qx ÷ 1
t(Ø)
-75
50
175
50
ps
ps
NOTE 2, 4
CLK1, nCLK1
Output Skew;
NOTE ꢀ, 4
CLK0, nCLK0
CLK1, nCLK1
tsk(o)
PLL_SEL = 0V
fOUT > 40MHz
40
ꢀ0
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
45
1
ps
ms
ps
ꢁ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢁ to 80ꢁ
400
40
800
60
50
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE ꢀ: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢁ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
15.625
250
MHz
Propagation Delay,
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V
f ≤ 250MHz, Qx ÷ 2
5.ꢀ
6.7
ns
Static Phase Offset; CLK0, nCLK0
PLL_SEL = 2.5V
fREF ≤ 167MHz, Qx ÷ 1
t(Ø)
-175
-25
125
45
ps
ps
NOTE 2, 4
CLK1, nCLK1
Output Skew;
NOTE ꢀ, 4
CLK0, nCLK0
CLK1, nCLK1
tsk(o)
PLL_SEL = 0V
fOUT > 40MHz
40
ꢀ5
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
45
1
ps
ms
ps
ꢁ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢁ to 80ꢁ
400
44
700
56
50
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE ꢀ: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87004AG
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REV. A JUNE 16, 2004
6
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢁ
1.25V 5ꢁ
SCOPE
SCOPE
VDD
,
VDD,
VDDA, VDDO
LVCMOS
GND
VDDA, VDDO
LVCMOS
GND
Qx
Qx
-1.65V 5ꢁ
-1.25V 5ꢁ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDO
Qx
Qy
2
nCLK0, nCLK1
VPP
VCMR
Cross Points
VDDO
2
CLK0, CLK1
GND
tsk(o)
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
VDDO
VDDO
2
VDDO
80ꢁ
tF
80ꢁ
tR
2
2
Q0:Qꢀ
➤
➤
20ꢁ
20ꢁ
t
cycle n+1
tcycle n
➤
➤
Clock
Outputs
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
87004AG
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REV. A JUNE 16, 2004
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ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
nCLK0,
nCLK1
CLK0,
CLK1
nCLK0,
nCLK1
VOH
VOL
VOH
CLK0,
CLK1
VDDO
2
VOL
VDDO
2
FB_IN
Q0:Qꢀ
➤
t(Ø)
➤
t
PD
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET
PROPAGATION DELAY
VDDO
2
VDDO
2
VDDO
2
Q0:Qꢀ
tPW
tPERIOD
tPW
tPERIOD
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87004AG
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REV. A JUNE 16, 2004
8
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS87004 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
ꢀ.ꢀV
VDD
.01µF
.01µF
10Ω
VDDA
10µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = ꢀ.ꢀV, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87004AG
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REV. A JUNE 16, 2004
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ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
87004AG
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REV. A JUNE 16, 2004
10
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC StandardTest Boards
70°C/W
6ꢀ°C/W
60°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87004 is: 2578
87004AG
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2004
11
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.ꢀ0
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.ꢀ0
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-15ꢀ
87004AG
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2004
12
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87004AG
Marking
Package
Count
60 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS87004AG
ICS87004AG
ICS87004AG
ICS87004AG
24 Lead TSSOP
ICS87004AGT
ICS87004AG
24 Lead TSSOP on Tape and Reel
24 Lead "Lead Free" TSSOP
60 per tube
2500
ICS87004AGT
24 Lead "Lead Free" TSSOP on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
87004AG
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2004
1ꢀ
ICS87004
Integrated
Circuit
Systems, Inc.
1:4, DIFFERENTIAL
-
TO-LVCMOS/LVTTL
ZERO
D
ELAY
C
LOCK
GENERATOR
REVISION HISTORY SHEET
Description of Change
Rev
Table
T8
Page
Date
A
1ꢀ
Ordering Information table - added "Lead-Free" part number.
6/16/04
87004AG
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2004
14
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