ICS8701 [ICSI]
LOW SKEW ±1, ±2 CLOCK GENERATOR; 低偏移± 1 ，± 2时钟发生器
| 型号： | ICS8701 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW ±1, ±2 CLOCK GENERATOR |
| 文件： | 总15页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8701 is a low skew, ÷1, ÷2 Clock Gen-
• 20 LVCMOS outputs, 7Ω typical output impedance
• 1 LVCMOS clock input
erator and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS out-
• Maximum output frequency up to 250MHz
puts are designed to drive 50Ω series or par-
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
• Output skew: 250ps (maximum)
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
The ICS8701 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
1
÷1
CLK
QAO - QA4
0
÷2
48 47 46 45 44 43 42 41 40 39 38 37
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
1
36
35
34
33
32
31
30
29
28
27
26
25
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
2
1
0
3
QB0 - QB4
QC0 - QC4
QD0 - QD4
4
5
6
ICS8701
7
1
0
8
9
10
11
12
1
0
13 14 15 16 17 18 19 20 21 22 23 24
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
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REV. B AUGUST 2, 2001
1
ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
2, 5,
Name
Type
Description
11, 26,
32, 35,
41, 44
7, 9, 18,
21, 28, 30,
37, 39, 46,
48
VDDO
Power
Power
Output supply pins. Connect to 3.3V or 2.5V.
GND
VDD
Power supply ground. Connect to ground.
16, 20
Power
Output
Positive supply pins. Connect to 3.3V.
25, 27,
29,
31, 33
34, 36,
38,
40, 42
43, 45,
47,
1, 3
4, 6,
8,
10, 12
QA0, QA1,
QA2,
QA3, QA4
QB0, QB1,
QB2,
QB3, QB4
QC0, QC1,
QC2,
QC3, QC4
QD0, QD1,
QD2,
Bank A outputs. LVCMOS interface levels.
7
typical output impedance.
Bank B outputs. LVCMOS interface levels.
typical output impedance.
Output
Output
Output
7
Bank C outputs. LVCMOS interface levels.
typical output impedance.
7
Bank D outputs. LVCMOS interface levels
typical output impedance.
7
QD3, QD4
22
CLK
Input
Input
Pulldown LVCMOS / LVTTL clock input.
Controls frequency division for bank D outputs.
LVCMOS interface levels.
13
DIV_SELD
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Controls frequency division for bank C outputs.
LVCMOS interface levels.
Controls frequency division for bank B outputs.
LVCMOS interface levels.
Controls frequency division for bank A outputs.
LVCMOS interface levels.
14
23
DIV_SELC
DIV_SELB
DIV_SELA
Input
Input
Input
Input
Input
24
BANK_EN1,
BANK_EN0
17, 19
15
Enables and disables outputs by banks. LVCMOS interface levels.
Master reset and output enable. Enables and disables all outputs.
LVCMOS interface levels.
nMR/OE
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK
4
pF
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, NMR/OE,
BANK_EN1,
CIN
Input Capacitance
4
RPULLUP
Input Pullup Resistor
51
51
K
RPULLDOWN Input Pulldown Resistor
K
VDD, VDDO = 3.465V
pF
CPD
Power Dissipation Capacitance
(per output)
VDD = 3.465V,
VDDO = 2.625V
pF
ROUT
Output Impedance
7
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Qx
nMR/OE BANK_EN1 BANK_EN0 DIV_SELx QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
frequency
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
0
1
1
1
1
1
1
1
1
X
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Hi Z
Hi Z
Hi Z
Active
Active
Hi Z
Hi Z
Active
Hi Z
Active
Active
Active
Hi Z
Hi Z
fIN
Active
Active
Hi Z
fIN
Active
fIN
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
47.9°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VDDO
VDD = VIH = 3.465V
VIL = 0V
IDD
Quiescent Power Supply Current
95
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
2
3.8
3.8
0.8
1.3
5
V
V
Input
VIH
High Voltage
CLK
2
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
VDD = 3.465V
VDD = 3.465V
-0.3
-0.3
V
Input
VIL
Low Voltage
CLK
V
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
VDD = V = 3.465V
µA
µA
µA
Input
IIH
IN
High Current
CLK
V
DD = V = 3.465V
150
IN
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
VDD = 3.465V, V = 0V
-150
Input
IIL
IN
Low Current
CLK
V
DD = 3.465V, V = 0V
-5
µA
V
IN
VDD = VDDO = 3.135V
OH = -36mA
VDD = VDDO = 3.135V
OL = 36mA
VOH
VOL
Output High Voltage
Output Low Voltage
2.6
I
0.5
V
I
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA =0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Maximum Input Frequency
250
3.4
MHz
ns
tPD
Propagation Delay; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
0MHZ
f
200MHz
2.2
tsk(b)
tsk(o)
Measured on rising edge atVDDO/2
Measured on rising edge atVDDO/2
200
250
ps
ps
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge atVDDO/2
300
ps
tsk(pp)
Part-to-Part Skew; NOTE 5, 7 Measured on rising edge atVDDO/2
600
850
850
ps
ps
ps
tR
tF
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
30% to 70%
30% to 70%
280
280
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
0MHZ
f
200MHz
tCYCLE/2
2.5
ns
ns
ns
odc
Output Duty Cycle
f = 200MHz
f = 10MHz
2
3
Output Enable Time;
NOTE 6
tEN
6
Output Disable Time;
NOTE 6
tDIS
f = 10MHz
6
ns
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the 50% point of the input to the output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew at between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the cross points.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
V
V
VDDO
VDD = VIH = 3.465V
VIL = 0V
IDD
Quiescent Power Supply Current
95
mA
TABLE 4D. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
2
3.8
3.8
0.8
1.3
5
V
V
Input
VIH
High Voltage
CLK
2
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
VDD = 3.465V
-0.3
-0.3
V
Input
VIL
Low Voltage
CLK
V
DD = 3.465V
V
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
VDD = V = 3.465V
µA
µA
µA
Input
IIH
IN
High Current
CLK
V
DD = V = 3.465V
150
IN
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
VDD = 3.465V, V = 0V
-150
Input
IIL
IN
Low Current
CLK
V
DD = 3.465V, V = 0V
-5
µA
V
IN
VDD = 3.135V,
VDDO = 2.375
VOH
Output High Voltage
1.8
I
OH = -27mA
VDD = 3.135V,
DDO = 2.375
IOL = 27mA
VOL
Output Low Voltage
V
0.5
V
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Maximum Input Frequency
250
3.6
MHz
ns
tPD
Propagation Delay; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
0MHZ
f
200MHz
2.6
tsk(b)
tsk(o)
Measured on rising edge atVDDO/2
Measured on rising edge atVDDO/2
225
250
ps
ps
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge atVDDO/2
300
ps
tsk(pp)
Part-to-Part Skew; NOTE 5, 7 Measured on rising edge atVDDO/2
600
850
850
ps
ps
ps
tR
tF
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
30% to 70%
30% to 70%
280
280
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
0MHZ
f
200MHz
tCYCLE/2
2.5
ns
ns
ns
odc
Output Duty Cycle
f = 200MHz
f = 10MHz
2
3
Output Enable Time;
NOTE 6
tEN
6
Output Disable Time;
NOTE 6
tDIS
f = 10MHz
6
ns
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the 50% point of the input to the output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew at between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the cross points.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VDDO
VDD
SCOPE
LVCMOS
VDD = +1.65V
VDDO = 1.65V
Qx
GND = -1.65V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
VDDO
SCOPE
LVCMOS
Qx
VDDO = +1.25V
GND = -1.25V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
Qx
Qy
tsk(o)
FIGURE 2 - OUTPUT SKEW
PART 1
Qx
PART 2
Qy
tsk(pp)
FIGURE 3 - PART-TO-PART SKEW
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 4 - INPUT AND OUTPUT RISE AND FALL TIME
VCC/2
CLK
QAx, QBx,
QCx, QDx
tPD
FIGURE 5 - PROPAGATION DELAY
CLK, QAx, QBx,
QCx, QDx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 6 - odc & tPERIOD
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8701-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8701-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW
Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 20 * 32mW = 640mW
Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 640mW = 969.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.969W * 42.1°C/W = 110.8°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 48-pin LQFP, Forced Convection
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS8701
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LOW SKEW
÷1, ÷2
CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVCMOS output driver circuit and termination are shown in Figure 7.
VDDO
Q1
VOUT
RL
Ω
50
FIGURE 7 - LVCMOS DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
DD
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MAX
OH_MAX
L
DD_MAX
/R ) * (V
- V
)
OL_MAX
L
DD_MAX
OL_MAX
•
•
For logic high, V = V
= V
– 1.2V
OUT
OH_MAX
DD_MAX
For logic low, V = V
= V
– 0.4V
OUT
OL_MAX
DD_MAX
Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L= 32mW
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ICS8701
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LOW SKEW ÷1, ÷2
CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8701 is: 1743
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ICS8701
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LOW SKEW ÷1, ÷2
CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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ICS8701
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1, ÷2
CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8701CY
Marking
Package
48 Lead LQFP
Count
Temperature
0°C to 70°C
0°C to 70°C
ICS8701CY
ICS8701CY
250 per tray
1000
ICS8701CYT
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8701CY
www.icst.com/products/hiperclocks.html
REV. B AUGUST 2, 2001
15
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