ICS8702BYT [ICSI]
LOW SKEW ±1, ±2 CLOCK GENERATOR; 低偏移± 1 ，± 2时钟发生器
| 型号： | ICS8702BYT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW ±1, ±2 CLOCK GENERATOR |
| 文件： | 总12页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8702 is a very low skew, ÷1, ÷2 Clock 20 LVCMOS outputs, 7Ω typical output impedance
,&6
Generator and a member of the HiPerClockS
Output frequency up to 250 MHz
HiPerClockS™ family of High Performance Clock Solutions
from ICS. The ICS8702 is designed to trans-
150ps bank skew, 200ps output, 250ps multiple frequency
skew, 650ps part-to-part skew
late any differential signal levels to LVCMOS lev-
els. True or inverting, single-ended to LVCMOS translation
can be achieved with a resistor bias on the nCLK or CLK
inputs, respectively. The effective fanout can be increased
from 20 to 40 by utilizing the ability of the outputs to drive two
series terminated lines.
Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS levels without external bias networks
Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, supports enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
enabling and disabling of all outputs simultaneously.
Translates any single-ended input signal to inverted LVCMOS
levels with a resistor bias on CLK input
LVCMOS / LVTTLcontrol inputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew char-
acteristics make the ICS8702 ideal for those clock distribu-
tion applications demanding well defined performance and
repeatability.
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0°C to 70°C ambient operating temperature
Other divide values available on request
BLOCK DIAGRAM
PIN ASSIGNMENT
÷1
÷2
1
0
CLK
nCLK
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37
QC3
VDDO
QC4
1
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
36
35
34
33
32
31
30
29
28
27
26
25
QB1
2
VDDO
QB0
1
0
3
QD0
4
QA4
VDDO
QD1
5
VDD0
QA3
6
ICS8702
1
0
GND
QD2
7
GND
QA2
8
GND
QD3
9
GND
QA1
10
11
12
VDDO
QD4
VDDO
QA0
1
0
13 14 15 16 17 18 19 20 21 22 23 24
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
48-Lead LQFP
Y Package
Top View
8702
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REV. A - AUGUST 7, 2000
1
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
2, 5, 11, 26,
32, 35, 41, 44
VDDO
Power
Power
Output power supply. Connect to 3.3V or 2.5V.
7, 9, 28, 30,
37, 39, 46, 48
GND
Output power supply. Connect to ground.
16, 20
18
VDDI
GND
Power
Power
Input power supply. Connect to 3.3V.
Input power supply. Connect to ground.
25, 27, 29,
31, 33
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
QA0, QA1, QA2,
QA3, QA4
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
Output
Output
Output
Output
Bank A outputs. 7Ω typical output impedance.
Bank B outputs. 7Ω typical output impedance.
Bank C outputs. 7Ω typical output impedance.
Bank D outputs. 7Ω typical output impedance.
10, 12
22
21
13
14
23
24
CLK
Input
Input
Input
Input
Input
Input
Pulldown Non-inverting differential clock input. Accepts any differential levels.
nCLK
Pullup
Pullup
Pullup
Pullup
Pullup
Inverting differential clock input. Accepts any differential levels.
DIV_SELD
DIV_SELC
DIV_SELB
DIV_SELA
Controls frequency division for bank D outputs. LVCMOS interface levels.
Controls frequency division for bank C outputs. LVCMOS interface levels.
Controls frequency division for bank B outputs. LVCMOS interface levels.
Controls frequency division for bank A outputs. LVCMOS interface levels.
BANK_EN1,
BANK_EN0
17, 19
15
Input
Input
Pullup
Pullup
Enables and disables outputs by banks. LVCMOS interface levels.
Asynchronous master reset. Resets clock dividers. Enables and disables all
outputs. LVCMOS interface levels.
nMR/OE
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
RPULLUP
51
51
KΩ
KΩ
pF
RPULLDOWN Input Pulldown Resistor
VDDI, VDDO = 3.465V
CPD
Power Dissipation Capacitance
(per output)
VDDI = 3.465V, VDDO = 2.625V
pF
ROUT
Output Impedance
7
Ω
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
nMR/OE
BANK_EN1
BANK_EN0
DIV_SELx QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4
Qx frequency
zero
0
1
1
1
1
1
1
1
1
X
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Hi Z
Active
Active
Active
Active
Active
Active
Active
Active
fIN/2
fIN/2
fIN/2
fIN/2
fIN
Active
Active
Active
Hi Z
Hi Z
Hi Z
Active
Active
Hi Z
Hi Z
Active
Hi Z
Active
Active
Active
Hi Z
Hi Z
fIN
Active
Active
Hi Z
fIN
Active
fIN
8702
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REV. A - AUGUST 7, 2000
2
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs
Outputs
Qx0 thru Qx4
LOW
Input to Output Mode
Polarity
nMR/OE
CLK
nCLK
1
1
1
1
1
1
0
1
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
0
Biased; NOTE 1
LOW
1
Biased; NOTE 1
HIGH
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
LOW
Inverting
NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for
the single ended input. For LVCMOS input levels the recommended input bias network is a resistor to VDDI, a resistor of equal value to
ground and a 0.1µF capacitor from the input to ground. The resulting switch point is approximately VDD/2 ± 300mV.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
4.6V
Inputs
Outputs
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
0°C to 70°C
Ambient Operating Temperature
Storage Temperature
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
8702
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REV. A - AUGUST 7, 2000
3
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
Symbol
VDDI
VDDO
VIH
Parameter
Test Conditions
Minimum
3.135
3.135
2
Typical
3.3
Maximum Units
Input Power Supply Voltage
Output Power Supply Voltage
3.465
3.465
3.8
V
V
V
V
3.3
Input High Voltage
Input Low Voltage
All except CLK, nCLK
VDDI = 3.465V
VDDI = 3.135V
VIL
All except CLK, nCLK;
CLK, nCLK
-0.3
0.8
Peak-to-Peak Input
Voltage
VPP
0.15
1.8
1.3
2.4
1.3
V
V
V
LVPECL Levels
Common Mode Input
Voltage; NOTE 1
VCMR
CLK, nCLK
DCM, HSTL, LVDS, SSTL
Levels
0.31
All except CLK
CLK
VDDI = VIN = 3.465V
VDDI = VIN = 3.465V
VDDI = 3.465, VIN = 0V
VDDI = 3.465, VIN = 0
5
µA
µA
µA
µA
IIH
IIL
Input High Current
Input Low Current
150
All except CLK
CLK
-150
-5
VDDI = VIH = 3.465V
VIL = 0V
VDDI = VDDO = 3.135V
IOH = -36mA
VDDI = VDDO = 3.135V
IOL = 36mA
IDD
Quiescent Power Supply Current
Output High Voltage
70
mA
V
VOH
VOL
2.6
Output Low Voltage
0.5
V
NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4A are for VCCI =
3.3V. VCMR for LVPECL will vary 1:1 with VCCI. Common mode input voltage for DCM, HSTL, LVDS and SSTL is defined as the crossover
voltage. See Figure 1.
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
Symbol
fMAX
tpLH
tpHL
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Maximum Input Frequency
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
Bank Skew; NOTE 2
250
3.5
MHz
ns
0MHZ < f ≤ 200MHz
0MHZ < f ≤ 200MHz
2.2
2.2
3.5
ns
tsk(b)
tsk(o)
tsk(ω)
tsk(pp)
tR
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
30% to 70%
150
200
250
650
850
850
ps
ps
ps
ps
ps
ps
Output Skew; NOTE 3
Multiple Frequency Skew; NOTE 4
Part to Part Skew; NOTE 5
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
280
280
tF
30% to 70%
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
0MHZ < f < 200MHz
tCYCLE/2
2.5
ns
tPW
Output Pulse Width
f = 200MHz
f = 10MHz
f = 10MHz
2
3
6
6
ns
n
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
tDIS
n
NOTE 1: All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8702
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REV. A - AUGUST 7, 2000
4
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
2.375
2
Typical
3.3
Maximum Units
VDDI
VDDO
VIH
Input Power Supply Voltage
Output Power Supply Voltage
3.465
2.625
3.8
V
V
V
V
2.5
Input High Voltage
Input Low Voltage
All except CLK, nCLK
VDDI = 3.465V
VDDI = 3.135V
VIL
All except CLK, nCLK
CLK, nCLK
-0.3
0.8
Peak-to-Peak
Input Voltage
Common Mode
Input Voltage;
NOTE 1
VPP
0.15
1.3
LVPECL Levels
DCM, HSTL, LVDS, SSTL Levels
VDDI = VIN = 3.465V
1.8
2.4
1.3
5
VCMR
CLK, nCLK
0.31
All except CLK
CLK
µA
µA
µA
µA
IIH
IIL
Input High Current
Input Low Current
VDDI = VIN = 3.465V
150
All except CLK
CLK
VDDI = 3.465V, VIN = 0V
VDDI = 3.465V, VIN = 0V
-150
-5
VDDI = VIH = 3.465V
VIL = 0V
VDDI = 3.135V, VDDO = 2.375V
IOH = -27mA
VDDI = 3.135V, VDDO = 2.375V
IOL = 27mA
IDD
Quiescent Power Supply Current
Output High Voltage
70
mA
V
VOH
VOL
1.9
Output Low Voltage
0.5
V
NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4B are for VCCI =
3.3V. VCMR for LVPECL will vary 1:1 with VCCI. Common mode input voltage for DCM, HSTL, LVDS and SSTL is defined as the crossover
voltage. See Figure 1.
TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C
Symbol
fMAX
tpLH
tpHL
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Maximum Input Frequency
Propagation Delay, Low-to-High
Propagation Delay, High-to-Low
Bank Skew; NOTE 2
250
3.6
MHz
ns
0MHZ < f ≤ 200MHz
0MHZ < f ≤ 200MHz
2.3
2.3
3.6
ns
tsk(b)
tsk(o)
tsk(ω)
tsk(pp)
tR
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
Measured on rising edge at VDDO/2
30% to 70%
150
200
250
700
850
850
ps
ps
ps
ps
ps
ps
Output Skew; NOTE 3
Multiple Frequency Skew; NOTE 4
Part to Part Skew; NOTE 5
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
280
280
tF
30% to 70%
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
0MHZ < f < 200MHz
tCYCLE/2
2.5
ns
tPW
Output Pulse Width
f = 200MHz
f = 10MHz
f = 10MHz
2
3
6
6
ns
n
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
tDIS
n
NOTE 1: All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions.
NOTE 5: Defined as the skew at different outputs on different devices operating at the same supply voltages and with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
8702
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REV. A - AUGUST 7, 2000
5
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 1A, 1B - TIMING DIAGRAMS
CLK
nCLK
Qx, ÷1
Qx, ÷2
FIGURE 1A - ACTIVE, ÷1, ÷2
nMR/OE
CLK
n CLK
Qx, ÷1
Qx, ÷2
High Impedance
Active
FIGURE 1B - RESET TO ACTIVE, ÷1, ÷2
8702
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REV. A - AUGUST 7, 2000
6
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 2A, 2B, 2C - INPUT CLOCK WAVEFORMS
VDDI
CLK
CROSS POINTS
VPP
VCMR
nCLK
GND
FIGURE 2A - DCM, HSTL, LVDS, SSTL DIFFERENTIAL INPUT LEVELS
VDDI
CLK
CROSS POINTS
VCMR
VPP
nCLK
GND
FIGURE 2B - LVPECL DIFFERENTIAL INPUT LEVEL
VDDI
GND
CLK
or
nCLK
FIGURE 2C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL
8702
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REV. A - AUGUST 7, 2000
7
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 3A, 3B - TIMING WAVEFORMS
CLK
Vpp
nCLK
tPHL
tPLH
Q
VDDO/2
FIGURE 3A - PROPAGATION DELAYS
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
nMR/OE,
3.3V
BANK_ENx
BANK_ENx
Q
0V
tPHZ
tPLZ
tPZH
tPZL
VOH
VOH - 300mV
VDDO/2
VDDO/2
VOL
VOL + 300mV
Q
FIGURE 3B - DISABLE AND ENABLE TIMES
fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps
8702
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REV. A - AUGUST 7, 2000
8
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 4A, 4B- SKEW DEFINITIONS & WAVEFORMS
Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
Vpp
nCLK
Qx0
VDDO/2
VDDO/2
tsk(b)
tsk(b)
Qx4
VDDO/2
VDDO/2
FIGURE 4A - BANK SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal
load conditions.
CLK
Vpp
nCLK
QA0 - QA4
VDDO/2
VDDO/2
tsk(o)
tsk(o)
QB0 - QB4
QC0 - QC4
QD0 - QD4
VDDO/2
VDDO/2
FIGURE 4B - OUTPUT SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
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REV. A - AUGUST 7, 2000
9
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
FIGURE 4C, 4D- SKEW DEFINITIONS & WAVEFORMS
Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the same
temperature, supply voltages and with equal load conditions.
CLK
Vpp
nCLK
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
VDDO/2
VDDO/2
or
QD0 - QD4
in ÷1
tsk(w)
tsk(w)
VDDO/2
VDDO/2
QA0 - QA4,
QB0 - QB4,
QC0 - QC4,
or
FIGURE 4C - MULTIPLE FREQUENCY SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
QD0 - QD4
in ÷2
Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply
voltages and with equal load conditions.
CLK
Vpp
nCLK
PART 1 QA0 - QA4
QB0 - QB4
QC0 - QC4
VDDO/2
VDDO/2
QD0 - QD4
tsk(p)
tsk(p)
PART 2 QA0 - QA4
QB0 - QB4
QC0 - QC4
VDDO/2
VDDO/2
QD0 - QD4
FIGURE 4B - OUTPUT SKEW
fin = 200MHz, Vpp = 300mV, tr = tf = 200ps
8702
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REV. A - AUGUST 7, 2000
10
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX
e / 2
NOTE 4
D
NOTE 5, 7
D1
D/2
NOTE 3
-D-
-A, B, OR -D-
D1/2
b
NOTE 3
-B-
NOTE 3
-A-
E1
E
-A, B, OR -D-
N
O
T
E
5,
7
N
O
T
E
4
e
NOTES:
1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI
Y14.5-1982
2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY
AT BOTTOM OF PARTING LINE.
E/2
N/4 TIPS
0.20 C A-B
4X
D
3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE
BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM
E1/2
PLANE -H-
.
4. TO BE DETERMINED AT SEATING PLACE -C-
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION.
.
SEE DETAIL “A”
6. “N” IS THE TOTAL NUMBER OF TERMINALS.
7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE
-H-.
8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM
DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG
BOTTOM OF PACKAGE.
8 PLACES
11 / 13°
A
9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL
IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
10. CONTROLLING DIMENSION: MILLIMETER.
11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95
REGISTRATION MS-026, VARIATION BBC.
-H- NOTE 2 / / 0.10
C
ccc
-C-
SEE DETAIL “B”
12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT OF THE PACKAGE.
NOTE 9
b
ddd
M C A-B S D S
S
JEDEC VARIATION
Y
M
B
O
L
N
O
T
WITH LEAD FINISH
ALL DIMENSIONS IN MILLIMETERS
E
BBC
0.09 / 0.20
0.09 / 0.16
MIN.
NOM.
MAX.
1.60
0.15
1.45
A
A1
A2
D
b1
12
0.05
BASE METAL
1.35
1.40
9.00 BSC.
7.00 BSC.
9.00 BSC.
7.00 BSC.
0.60
4
D1
E
7, 8
4
0° MIN.
E1
L
7, 8
-
0.05 S
0.08/0.20 R.
0.25
GAUGE PLANE
DATUM
PLANE
-H-
0.45
0.75
A2
A1
N
48
e
0.5 BSC.
0.22
0.08
R. MIN.
b
9
0.17
0.17
0.27
0.23
0.08
0.08
0° - 7 °
b1
ccc
ddd
0.20
0.20 MIN.
L
1.00 REF.
8702
www.icst.com
REV. A - AUGUST 7, 2000
11
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
ORDERING INFORMATION
Part/Order Number
ICS8702BY
Marking
ICS8702BY
ICS8702BY
Package
48 Lead LQFP
Count
250 per tray
2000
Temperature
0°C to 70°C
0°C to 70°C
ICS8702BYT
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8702
www.icst.com
REV. A - AUGUST 7, 2000
12
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