ICS8725Y [ICSI]
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER; 差分至LVHSTL零延迟缓冲器
| 型号： | ICS8725Y |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER |
| 文件： | 总7页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8725 is a high performance LVHSTL
• Fully integrated PLL
,&6
zero delay buffer and a member of the
• 5 LVHSTL outputs each with the ability to drive 50Ω to
ground
HiPerClockS™
HiPerClockS™ family of High Performance
Clocks Solutions from ICS. The VCO operates
at a frequency range of 250MHz to 500MHz.
• Voh (max) = 1.2V
Utilizing one of the outputs as feedback to the PLL output
frequencies up to 500MHz can be regenerated with zero
delay with respect to the input. Dual reference clock inputs
support redundant clock or multiple reference applications.
• 31.25MHz to 500MHz output frequency range
• Spread Smart™ for regenerating spread spectrum clocks
• Differential reference clock inputs accept any differential
input signal
•· Differential reference clock inputs will accept single ended
input signal with one of the inputs biased with a resistor
network
• 31.25MHz to 622MHz input frequency range
• LVCMOS / LVTTL control inputs
• 3.3V core, 1.8V output operating supply voltage
• 32 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.8mm package lead pitch
• 0°C to 70°C ambient operating temperature
• Industrial temperature version available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
DIV_SEL0
32 31 30 29 28 27 26 25
DIV_SEL1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
DIV_SEL0
DIV_SEL1
REF_CLK1
nREF_CLK1
REF_CLK2
nREF_CLK2
REF_SEL
VDDO
Q3
÷1
÷2
÷4
REF_CLK1
nQ3
Q2
0
1
0
1
0
1
nREF_CLK1
ICS8725
REF_CLK2
nREF_CLK2
PLL
÷8
nQ2
Q1
÷8
REF_SEL
REF_DIV
nQ1
VDDO
MR
FB_IN
9
10 11 12 13 14 15 16
nFB_IN
PLL_SEL
MR
32-Lead LQFP
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
1
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
1
DIV_SEL0
Input
Determines output divider valued in Table 3.
LVCMOS / LVTTL interface levels.
2
DIV_SEL1
REF_CLK1
Input
Input
Pulldown
3
4
5
6
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
nREF_CLK1 Input
REF_CLK2
nRE2_CLK2
Input
Input
Pullup
Inverting differential clock input.
Differential clock select input. When Low selects REF_CLK2 or
nREF_CLK2. When HIGH selects REF_CLK1 or nREF_CLK1.
Resets dividers and determine state of the outputs.
LVCMOS / LVTTL interface levels.
7
8
REF_SEL
MR
Input
Input
Pulldown
Pulldown
9
VDDI
nFB_IN
FB_IN
Power
Input
Input
Input
Input and core power supply pin. Connect to 3.3V.
10
11
12
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown
REF_DIV
13, 28,
29
VEE
Power
Output
Power
Output
Output
Output
Ground pins. Connect to ground.
nQ0,
Q0
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
14, 15
16. 17,
24, 25
VDDO
Output power supply pins. Connect to 1.8V.
nQ1,
Q1
nQ2,
Q2
nQ3,
Q3
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
18, 19
20, 21
22, 23
nQ4,
Q4
Differential clock outputs. 50Ω typical output impedance.
LVHSTL interface levels.
26, 27
30
Output
Power
VDDA
PLL_SEL
VDDI
PLL power supply pin. Connect to 3.3V.
Selects between the PLL and the reference clock as the input to the
dividers. When HIGH select PLL. When LOW selects reference clock.
LVCMOS / LVTTL interface levels.
31
32
Input
Pullup
Power
Output power supply pin. Connect to 3.3V.
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
2
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK1,
nREF_CLK1,
REF_CLK2,
nREF_CLK2,
FB_IN, nFB_IN
DIV_SEL0,
TBD
TBD
pF
pF
Input
Capacitance
CIN
DIV_SEL1,
REF_SEL,
REF_DIV
PLL_SEL, MR
Input
Pullup Resistor
Input
RPULLUP
51
51
KΩ
KΩ
RPULLDOWN
Pulldown Resistor
TABLE 3. CONTROL INPUTS FUNCTION TABLE
FREQUENCY (MHz)
DIV_SEL1
DIV_SEL0
MINIMUM
MAXIMUM
250
0
0
1
1
0
1
0
1
250
125
250
62.5
31.25
125
62.5
TABLE 4. PLL INPUT REFERENCE CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol
fREF
tR
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Reference Frequency
Input Rise Time
20
250
TBD
TBD
TBD
MHz
ns
Measured at 20% to 80% points
Measured at 20% to 80% point
tF
Input Fall Time
ns
tDC
Input Reference Duty Cycle
TBD
%
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
3
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Inputs
Outputs
4.6V
-0.5V to VDD+0.5 V
-0.5V to VDD+0.5V
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any conditions beyond those listed in the DC Character-
istics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDDI
VDDA
VDDO
IEE
Input Power Supply Voltage
3.135
3.135
3.3
3.3
1.8
3.465
3.465
V
V
Analog Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
V
mA
TABLE 5B. DIFFERENTIAL DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
REF_CLK1, REF_CLK2,
FB_IN
nREF_CLK1, nREF_CLK2,
nFB_IN
VIN = 3.465V
VIN = 3.465V
150
5
µA
µA
IIH
Input High Current
REF_CLK1, REF_CLK2,
FB_IN
VIN = 0V
VIN = 0V
-5
µA
µA
IIL
Input Low Current
nREF1, nREF2, nFB_IN
-150
NOTE: For REF_CLK1, nREF_CLK1 and REF_CLK2, nREF_CLK2 input levels, see VPP and VCMR in AC Characteristics
table.
TABLE 5C. LVCMOS DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SEL0, DIV_SEL1,
VIH
VIL
Input High Voltage REF_SEL, PLL_SEL,
REF_DIV, MR
DIV_SEL0, DIV_SEL1,
Input Low Voltage REF_SEL, PLL_SEL,
REF_DIV, MR
2
3.765
0.8
V
V
-0.3
DIV_SEL0, DIV_ SEL1,
REF_DIV, REF_SEL, MR
VIN = 3.465V
VIN = 3.465V
VIN = 0V
150
5
µA
µA
µA
µA
IIH
IIL
Input High Current
Input Low Current
PLL_SEL
DIV_SEL0, DIV_ SEL1,
REF_DIV, REF_SEL, MR
-5
PLL_SEL
VIN = 0V
-150
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
4
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
TABLE 5D. LVHSTL DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
1.2
Units
VOH
VOL
Output High Voltage; NOTE 1
1.0
0
V
V
Output Low Voltage; NOTE 1
Output Crossover Voltage
0.4
40% x (VOH-VOL)
+ VOL
60% x (VOH-VOL)
+ VOL
VOX
V
NOTE 1: Outputs terminated with 50Ω to ground. The power dissipation of a terminated output pair is 32mW.
TABLE 6. AC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
VPP
Maximum Output Frequency
500
MHz
Peak-to-Peak Input Voltage
Common Mode Input Voltage
f = 500MHz
f = 500MHz
VCMR
Propagation Delay,
Low-to-High
Propagation Delay,
High-to-Low
tpLH
tpHL
PLL_SEL=0V, 0MHz ≤ f ≤ 500MHz
PLL_SEL=0V, 0MHz ≤ f ≤ 500MHz
TBD
TBD
TBD
TBD
ns
ns
REF_CLK1,
PLL Reference
nREF_CLK1
PLL_SEL=3.3V, fREF=TBD,
fVCO=TBD
t(Ø)
Zero Delay;
-100
TBD
100
100
ps
REF_CLK2,
nREF_CLK2
NOTE 2
Measured on rising edge at
VDDO/2
Measured on rising edge at
VDDO/2
tsk(o)
tjit(cc)
Output Skew; NOTE 3
Cycle-to-Cycle Jitter
ps
ps
±100
tL
tR
tF
PLL Lock Time
Output Rise Time
Output Fall Time
TBD
TBD
TBD
TBD
TBD
ps
ps
tCYCLE/2
-TBD
tCYCLE/2
+TBD
0MHz ≤ f ≤ 500MHz
tCYCLE/2
2.08
ns
tPW
Output Pulse Width
f = 500MHz
TBD
TBD
TBD
TBD
ns
ns
ns
tEN
Output Enable Time
Output Disable Time
tDIS
NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent pairs
of cycles.
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
5
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
D
D2
θ
32
25
24
1
2
3
L
E
E1
E2
N
8
17
16
9
e
D1
A
C
A2
SEATING
PLANE
-C-
ccc
b
A1
c
TABLE 7. PACKAGE DIMENISIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
6
PRELIMINARY
ICS8725
Integrated
Circuit
Systems, Incꢀ
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8725Y
Marking
ICS87251
ICS8725
Package
32 Lead LQFP
Count
250 per tray
2000
Temperature
0°C to 70°C
0°C to 70°C
ICS8725YT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
7
相关型号：
ICS873032AGLF
Low Skew Clock Driver, 873032 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8
IDT
ICS873032AMLF
Low Skew Clock Driver, 873032 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8
IDT
ICS873032AMLFT
Low Skew Clock Driver, 873032 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8
IDT
©2020 ICPDF网 联系我们和版权申明