ICS8737-11 [ICSI]
LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR; 低偏移± 1 / ± 2差分至3.3V的LVPECL时钟发生器
| 型号： | ICS8737-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR |
| 文件： | 总13页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8737-11 is a low skew, high performance • 2 divide by 1 differential 3.3V LVPECL outputs;
Differential-to-3.3V LVPECL Clock Generator/
Divider and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8737-11 has two selectable clock
2 divide by 2 differential 3.3V LVPECLoutputs
HiPerClockS™
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
inputs. The CLK, nCLK pair can accept most standard differ-
ential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels.The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVPECL levels with resistor bias on nCLK input
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
• Output skew: 60ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Bank skew: Bank A - 20ps (maximum),
Bank B - 35ps (maximum)
• Propagation delay: 1.7ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
nQA0
VEE
CLK_EN
CLK_SEL
CLK
1
2
3
4
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
VCC
QA1
nQA1
QB0
nQB0
VCC
D
CLK_EN
QA1
nQA1
Q
LE
5
nCLK
PCLK
nPCLK
nc
CLK
nCLK
PCLK
nPCLK
÷1
÷2
6
7
8
9
0
1
MR
VCC
QB1
nQB1
QB0
nQB0
10
CLK_SEL
MR
ICS8737-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
QB1
nQB1
Top View
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ICS8737-11
Integrated
Circuit
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LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VEE
Power
Power
Negative supply pin. Connect to ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
Clock Select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK inputs. LVTTL / LVCMOS interface levels.
2
CLK_EN
Pullup
Pulldown
3
CLK_SEL
Input
4
CLK
nCLK
PCLK
nPCLK
nc
Input
Input
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential LVPECL clock input.
5
6
Input
7
Input
Pullup
Inverting differential LVPECL clock input.
No connect.
8
Unused
Input
9
MR
Pulldown Master reset. Resets the output divider.
Positive supply pins. Connect to 3.3V.
10, 13, 18
11, 12
14, 15
16, 17
19, 20
VCC
Power
nQB1, QB1 Output
nQB0, QB0 Output
nQA1, QA1 Output
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
CLK, nCLK
4
4
pF
pF
PCLK, nPCLK
CIN
Input Capacitance
CLK_SEL,
4
pF
CLK_EN, MR
RPULLUP
Input Pullup Resistor
51
51
K
K
RPULLDOWN Input Pulldown Resistor
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ICS8737-11
Integrated
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LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
MR CLK_EN CLK_SEL Selected Source QA0 thru QA1 nQA0 thru nQA1 QB0 thru QB1 nQB0 thru nQB1
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
X
LOW
HIGH
Disabled; HIGH
Disabled; HIGH
Enabled
LOW
HIGH
Disabled; HIGH
Disabled; HIGH
Enabled
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Disabled; LOW
Disabled; LOW
Enabled
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Enabled
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown if Figure 1.
In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described
in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQA0 - nQA1,
nQB0 - nQB1
QA0 - QA1,
QB0 - QB1
FIGURE 1: CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK or PCLK
nCLK or nPCLK
QAx
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQAx
HIGH
LOW
HIGH
LOW
LOW
HIGH
QBx
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQBx
HIGH
LOW
HIGH
LOW
LOW
HIGH
0
0
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring differential input to
accept single ended levels.
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ICS8737-11
Integrated
Circuit
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LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
73.2°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
IEE
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
CLK_EN, CLK_SEL, MR
CLK_EN, CLK_SEL, MR
2
3.765
0.8
V
-0.3
V
CLK_EN
VIN = VCC = 3.465V
VIN = VCC = 3.465V
5
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
CLK_SEL, MR
CLK_EN
150
VIN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
-150
-5
IIL
CLK_SEL,MR
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
5
µA
µA
µA
µA
V
VIN = VCC = 3.465V
150
nCLK
CLK
VIN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
V
EE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
Minimum Typical
Maximum Units
150
5
µA
µA
µA
µA
V
V
-5
IIL
Input Low Current
VIN = 0V, VCC = 3.465V
-150
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
VOH
Common Mode Input Voltage; NOTE 1, 2
Output High Voltage; NOTE 3
VEE + 1.5
VCC - 1.4
VCC - 2.0
0.65
VCC
V
VCC - 1.0
VCC - 1.7
0.9
V
VOL
Output Low Voltage; NOTE 3
V
VSWING
Peak-to-Peak Output Voltage Swing
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Maximum Output Frequency
650
1.7
1.6
60
MHz
ns
CLK, nCLK
1.3
1.2
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 4
ƒ 650MHz
PCLK, nPCLK
tsk(o)
tsk(b)
ps
ps
Bank A
Bank B
20
35
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
200
700
700
52
ps
ps
ps
%
tR
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
48
tF
Output Fall Time
odc
Output Duty Cycle
50
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8737-11
Integrated
Circuit
Systems, Incꢀ
LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
VCC
SCOPE
Qx
LVPECL
VCC = 2.0V
nQx
VEE = -1.3V ± 0.135V
FIGURE 2 - OUTPUT LOAD TEST CIRCUIT
VCC
CLK, PCLK
VPP
VCMR
Cross Points
nCLK, nPCLK
VEE
FIGURE 3 - DIFFERENTIAL INPUT LEVEL
Qx
nQx
Qy
nQy
tsk(o)
FIGURE 4 - OUTPUT SKEW
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ICS8737-11
Integrated
Circuit
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LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Qx
PART1
nQx
Qy
PART2
nQy
tsk(pp)
FIGURE 5 - PART-TO-PART SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 6 - INPUT AND OUTPUT RISE AND FALL TIME
CLK, PCLK
nCLK, nPCLK
Q0A0, Q0A1 -
Q0B0, Q0B1
nQ0A0, nQ0A1 -
nQ0B0, nQ0B1
tPD
FIGURE 7 - PROPAGATION DELAY
CLK, PCLK
nCLK, nPCLK
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 8 - odc & tPERIOD
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~
VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to
the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input
voltage swing. For example, if the input clock swing is only 12.5V and VCC = 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
VCC
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8737-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8737-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 50mA= 173.25mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power_MAX (3.465V, with all outputs switching) = 173.25mW + 120.8mW = 294.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.294W * 66.6°C/W = 89.58°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 20-pin TSSOP, Forced Convection
θ
by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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LOW SKEW
÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 10.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
)
OH_MAX
OH_MAX
CC_MAX
L
CC_MAX
– (V
- 2V))/R ] * (V
- V
OL_MAX
)
OL_MAX
CC_MAX
L
CC_MAX
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CC_MAX
Using V
= 3.465, this results in V
= 2.465V
= 1.765V
CC_MAX
OH_MAX
OL_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
Using V
= 3.465, this results in V
CC_MAX
Pd_H = [(2.465V - (3.465V - 2V))/50 Ω] * (3.465V - 2.465V) = 20.0mW
Pd_L = [(1.765V - (3.465V - 2V))/50 Ω] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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LOW SKEW
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θ
by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8737-11 is: 510
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PACKAGE OUTLINE - G SUFFIX
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8737AG-11
Marking
Package
Count
72
Temperature
0°C to 70°C
0°C to 70°C
ICS8737AG-11
ICS8737AG-11
20 lead TSSOP
ICS8737AG-11T
20 lead TSSOP on Tape and Reel
2500
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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SI9137LG
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SI9122E
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