ICS873990AYLFT_技术文档

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

FEATURES

GENERAL DESCRIPTION

• 14 differential LVPECL outputs

The ICS873990 is a low voltage, low skew, 3.3V

ICS

LVPECL/ECL Clock Generator and a member

of the HiPerClockS™family of High Performance

• Selectable crystal oscillator interface or TEST_CLK inputs

HiPerClockS™

Clock Solutions from ICS. The ICS873990 has • TEST_CLK accepts the following input levels:

two selectable clock inputs. The XTAL1 and

LVCMOS, LVTTL

XTAL2 are used to interface to a crystal and the TEST_CLK

pin can accept a LVCMOS or LVTTL input. This device has a

fully integrated PLL along with frequency configurable out-

puts. An external feedback input and output regenerates

clocks with “zero delay”.

• Output frequency: 400MHz (maximum)

• Crystal input frequency range: 10MHz to 25MHz

• VCO range: 200MHz to 800MHz

• Output skew: 250ps (maximum)

• Cycle-to-cyle jitter: 50ps (typical)

The four independent banks of outputs each have their own

output dividers, which allow the device to generate a multi-

tude of different bank frequency ratios and output-to-input

frequency ratios. The output frequency range is 25MHz to

400MHz and the input frequency range is 6.25MHz to

125MHz.The PLL_SEL input can be used to bypass the PLL

for test and system debug purposes. In bypass mode, the

input clock is routed around the PLL and into the internal out-

put dividers.

• LVPECL mode operating voltage supply range:

V_CC= 3.135V to 3.465V, V_EE= 0V

• ECL mode operating voltage supply range:

V_CC= 0V, V_EE= -3.465V to -3.135V

• 0°C to 70°C ambient operating temperature

• Industrial temperature available upon request

• Lead-Free package fully RoHS compliant

The ICS873990 also has a SYNC output which can be used

for system synchronization purposes. It monitors Bank A and

Bank C outputs for coincident rising edges and signals a pulse

per the timing diagrams in this data sheet.This feature is used

primarily in applications where Bank A and Bank C are run-

ning at different frequencies, and is particularly useful when

they are running at non-integer multiples of each other.

PIN ASSIGNMENT

Example Applications:

1. Line Card Multiplier: Multiply 19.44MHz from a back-plane

to 77.76MHz on the line card ASIC and Serdes.

39 38 37 36 35 34 33 32 31 30 29 28 27

nQB3

QB3

40

41

42

43

44

45

46

47

48

49

50

51

52

26

25

24

23

22

21

20

19

18

17

16

15

14

QC1

2. Zero Delay Buffer: Fan out up to thirteen 100MHz copies

from a reference clock to multiple processing units on an

embedded system.

nQC1

QC0

V^CCO

nQA0

nQC0

V^CCO

QD1

QA0

nQA1

QA1

ICS873990

nQD1

QD0

nQA2

QA2

nQD0

V^CCO

QFB

nQFB

V^CCA

nQA3

QA3

SYNC_SEL

VCO_SEL

1

2

3

4

5

6

7 8 9 10 11 12 13

52-Lead LQFP

10mm x 10mm x 1.4mm package body

Y package

TopView

873990AY

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REV. B JUNE 13, 2005

1

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

BLOCK DIAGRAM

Pulldown

VCO_SEL

PLL_EN

QA0

REF_SEL

TEST_CLK

XTAL_IN

nQA0

Pulldown

QA1

nQA1

QA2

XTAL

OSC

XTAL_OUT

PHASE

DETECTOR

VCO

nQA2

QA3

EXT_FB

LPF

nQA3

nEXT_FB

QB0

nQB0

Pulldown

MR

QB1

nQB1

FREQUENCY

GENERATOR

QB2

nQB2

Pulldown

FSEL_0:3

QB3

SYNC

nQB3

QC0

FSEL_FB0:2

nQC0

QC1

nQC1

QC2

nQC2

QD0

nQD0

Pulldown

SYNC_SEL

QD1

nQD1

QFB

nQFB

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

V_EE

Power

Negative supply pin.

Active High Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs (Qx) to go low and the inverted outputs

(nQx) to go high. When logic LOW, the internal dividers and the

outputs are enabled. LVCMOS/LVTTL interface levels.

2

MR

Input

Pulldown

PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH,

PLL is in bypass mode. LVCMOS/LVTTL interface levels.

Selects between the different reference inputs as the PLL reference

3

4

PLL_EN

Input

Pulldown

REF_SEL

Pulldown source. When logic LOW, selects crystal inputs. When logic HIGH,

selects TEST_CLK. LVCMOS/LVTTL interface levels.

5

6

7

FSEL_FB2

FSEL_FB1

FSEL_FB0

Input

Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.

8

TEST_CLK

Input

Pulldown LVCMOS/LVTTL test clock input.

XTAL_IN,

XTAL_OUT

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the

output.

9, 10

11

12

V_CC

Power

Input

Core supply pin.

EXT_FB

Pulldown External feedback input.

Pullup/

13

14

nEXT_FB

V_CCA

Input

Power

Output

Power

External feedback input. V_CC/2 default when left floating.

Pulldown

Analog supply pin.

15,

16

nQFB,

QFB

Differential feedback output pair. LVPECL interface levels.

17, 22, 30, 42

18, 19

V_CCO

Output supply pins.

nQD0, QD0 Output

nQD1, QD1 Output

nQC0, QC0 Output

Differential output pair. LVPECL interface levels.

20, 21

23, 24

25, 26

nQC1, QC1 Output

FSEL3

FSEL2

FSEL1

FSEL0

27

33

36

39

Input

Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.

28, 29

31, 32

34, 35

37, 38

40, 41

43, 44

45, 46

47, 48

49, 50

nQC2, QC2 Output

Differential output pair. LVPECL interface levels.

nQB0, QB0

Output

nQB1, QB1 Output

nQB2, QB2 Output

nQB3, QB3

nQA0, QA0

Output

nQA1, QA1 Output

nQA2, QA2 Output

nQA3, QA3

SYNC_SEL

VCO_SEL

Output

Input

Sync output select pin. When LOW, the SYNC output follows the

Pulldown

51

52

timing diagram (page 5). When HIGH, QD output follows QC output.

Input

Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

873990AY

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REV. B JUNE 13, 2005

3

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

C_IN

R_PULLDOWNInput Pulldown Resistor

R_PULLupInput Pullup Resistor

Input Capacitance

4

pF

kΩ

51

TABLE 3A. SELECT PIN FUNCTION TABLE

Inputs

TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE

Inputs

Outputs

QFB

÷2

Outputs

FSEL_FB2 FSEL_FB1 FSEL_FB0

FSEL3 FSEL2 FSEL1 FSEL0 QAx QBx QCx

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

÷ 2

÷ 4

÷ 6

÷ 8

÷ 2

÷ 4

÷ 2

÷ 6

÷ 4

÷ 6

÷ 2

÷ 8

÷ 4

÷ 6

÷ 8

÷ 2

÷ 4

÷ 6

÷ 8

÷ 6

÷ 8

÷4

÷6

÷8

÷16

÷24

÷32

TABLE 3C. INPUT CONTROL FUNCTION TABLE

Control Input Pin

PLL_EN

Logic 0

Enables PLL

fVCO

Logic 1

Bypasses PLL

fVCO/2

VCO_SEL

REF_SEL

MR

Selects XTAL

---

Selects TEST_CLK

Resets outputs

Match QC Outputs

SYNC_SEL

Selects outputs

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REV. B JUNE 13, 2005

4

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

1:1 Mode

QA

QC

SYNC (QD)

2:1 Mode

QA

QC

SYNC (QD)

3:1 Mode

QA

QC

SYNC (QD)

3:2 Mode

QA

QC

SYNC (QD)

4:3 Mode

QA

QC

SYNC (QD)

FIGURE 1. TIMING DIAGRAMS

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses beyond those listed under Absolute Maximum

Ratings may cause permanent damage to the device. These

ratings are stress specifications only. Functional operation of

product at these conditions or any conditions beyond those listed

in the DC Characteristics or AC Characteristics is not implied.

Exposure to absolute maxi-mum rating conditions for extended

periods may affect product reliability.

SupplyVoltage, V

4.6V

CC

Inputs, V

-0.5V to V_CC+ 0.5 V

I

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

PackageThermal Impedance, θ

42.3°C/W (0 lfpm)

-65°C to 150°C

JA

StorageTemperature, T

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5ꢀ, V_EE= 0V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum Units

V_CC

V_CCA

V_CCO

I_CC

Core Supply Voltage

3.465

150

V

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

3.135

3.3

3.135

3.3

V

mA

I_CCA

I_CCO

15

95

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5ꢀ, V_EE= 0V, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

REF_SEL, SYNC_SEL,

FSEL_FB0:FB2, PLL_EN,

FSEL0:3, MR, VCO_SEL

2

V

_CC+ 0.3

V

Input

V_IH

High Voltage

TEST_CLK

2

V_CC+ 0.3

0.8

REF_SEL, SYNC_SEL,

FSEL_FB0:FB2, PLL_EN,

FSEL0:3, MR, VCO_SEL

-0.3

Input

V_IL

Low Voltage

TEST_CLK

1.3

V

I_IH

I_IL

Input High Current

Input Low Current

V_CC= V_IN= 3.465V

150

µA

V_IN= 0V, V_CC= 3.465V

-5

TABLE 4B. LVPECL DC CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5ꢀ, V_EE= 0V, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_OH

Output High Voltage, NOTE 1

V_CC- 1.4

V_CC- 2.0

0.6

V_CC- 0.9

V_CC- 1.7

1.0

V

V_OL

Output Low Voltage, NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

TABLE 5. CRYSTAL CHARACTERISTICS

Parameter

Test Conditions

Minimum Typical Maximum

Units

Mode of Oscillation

Frequency

Fundamental

10

25

50

7

MHz

Ω

Equivalent Series Resistance (ESR)

Shunt Capacitance

Drive Level

pF

1

mW

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

t_R/ t_RInput Rise/Fall Time TEST_CLK

Test Conditions

Minimum Typical Maximum Units

3

133.33

100

50

ns

Feedback ÷ 6

Feedback ÷ 8

Feedback ÷ 16

Feedback ÷ 24

Feedback ÷ 32

Feedback ÷ 4

Feedback ÷ 6

Feedback ÷ 8

Feedback ÷ 16

Feedback ÷ 24

Feedback ÷ 32

66.66

50

MHz

ꢀ

Reference Frequency

VCO_SEL = 0

25

16.66

12.5

50

33.33

25

f_REF

100

66.66

50

33.33

25

Reference Frequency

VCO_SEL = 1

12.5

8.33

6.25

25

16.66

12.5

75

f_REFDC

Reference Input Duty Cycle

NOTE:These parameters are guaranteed by design, but not tested in production.

TABLE 7. AC CHARACTERISTICS, V_CC= V_CCA= V_CCO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

f_MAX

Output Frequency

400

MHz

Static Phase Offset;

NOTE 1, 5

Output Skew; NOTE 2, 3

t(Ø)

TEST_CLK

-240

120

50

0

ps

tsk(o)

tsk(w)

tjit(cc)

250

350

ps

Multiple Frequency Skew; NOTE 3, 6

Cycle-to-Cycle Jitter; NOTE 3

ps

VCO_SEL = 0

VCO_SEL = 1

400

200

800

400

10

MHz

ms

ns

f_VCO

PLL VCO Lock Range; NOTE 4

t_LOCK

t_R/ t_F

odc

PLL Lock Time

Output Rise/Fall Time

Output Duty Cycle

20ꢀ to 80ꢀ

0.2

45

1

55

ꢀ

All parameters measured at f_MAXunless noted otherwise.

NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal

when the PLL is locked and the input reference frequency is stable.

NOTE 2:Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4 and some ÷6.

When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2.

NOTE 5: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8.

NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies

with the same supply voltages and equal load conditions. Measured at V_CCO/2.

873990AY

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

PARAMETER MEASUREMENT INFORMATION

2V

nQx

Qx

SCOPE

Qx

V_CC

V_CCA, V_CCO

,

LVPECL

nQy

Qy

nQx

V_EE

tsk(o)

-1.3V -0.165V

OUTPUT LOAD AC TEST CIRCUIT

OUTPUT SKEW

nQFB,

nQAx:nQDx

V_OH

V_OL

TEST_CLK

QFB,

QAx:QDx

nQFB,

nQAx:nQDx

➤

tcycle n

tcycle n+1

➤

V_OH

V_OL

➤

QFB,

QAx:QDx

➤

t(Ø)

➤

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

STATIC PHASE OFFSET

CYCLE-TO-CYCLE JITTER

nQFB,

nQAx:nQDx

nQxx

Qxx

QFB,

QAx:QDx

t_PW

t_PERIOD

nQyy

Qyy

t_PW

odc =

x 100ꢀ

tsk(ω)

t_PERIOD

MULTIPLE FREQUENCY SKEW

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

80ꢀ

t_F

80ꢀ

V_SWING

20ꢀ

Clock

20ꢀ

Outputs

t_R

OUTPUT RISE/FALL TIME

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise.The ICS873990 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V_CC, V_CCA, and V_CCO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 2 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V_CCApin.

3.3V

V_CC

.01μF

10Ω

V_CCA

10μF

FIGURE 2. POWER SUPPLY FILTERING

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs.The two different layouts mentioned

are recommended only as guidelines.

50Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion. Figures 3A and 3B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs.Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

3.3V

Z_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

1

RTT =

Z_o

RTT

84Ω

((V_OH+ V_OL) / (V_CC– 2)) – 2

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

CRYSTAL INPUT INTERFACE

The ICS873990 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown

in Figure 4 below were determined using a 25MHz, 18pF par-

allel resonant crystal and were chosen to minimize the ppm

error.The optimum C1 and C2 values can be slightly adjusted

for different board layouts.

XTAL_OUT

XTAL_IN

C1

22p

X1

18pF Parallel Crystal

C2

22p

Figure 4. CRYSTAL INPUt INTERFACE

873990AY

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS873990.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS873990 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.3V + 5ꢀ = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 165mA = 571.7mW

Power (outputs)_MAX= 30mW/Loaded Output pair

If all outputs are loaded, the total power is 14 * 30mW = 420mW

Total Power_{_MAX}(3.465V, with all outputs switching) = 571.7mW + 420mW = 991.7mW

2. JunctionTemperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device.The maximum recommended junction temperature for HiPerClockS^TMdevices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = JunctionTemperature

θ_JA= Junction-to-Ambient Thermal Resistance

Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)

T_A= AmbientTemperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 47.1°C/W perTable 8 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.992W * 47.1°C/W = 116.7°C. This is below the limit of 125°C.

This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 8. THERMAL RESISTANCE θ_JAFOR 52-PIN LQFP, FORCED CONVECTION

θ_JAbyVelocity (Linear Feet per Minute)

0

200

47.1°C/W

36.4°C/W

500

42.0°C/W

34.0°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

58.0°C/W

42.3°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 5.

V_CCO

Q1

V_OUT

R L

50

V_CCO- 2V

FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage ofV - 2V.

CCO

•

For logic high, V_OUT= V

= V

– 0.9V

OH_MAX

CCO_MAX

)

= 0.9V

OH_MAX

(V

- V

CCO_MAX

For logic low, V_OUT= V

= V

– 1.7V

OL_MAX

CCO_MAX

)

= 1.7V

OL_MAX

(V

- V

CCO_MAX

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

))

Pd_H = [(V

– (V

- 2V))/R ] * (V

- V

) = [(2V - (V

- V

/R ] * (V

- V

) =

OH_MAX

CCO_MAX

OH_MAX

CCO_MAX

OH_MAX

CCO_MAX

OH_MAX

L

[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW

))

Pd_L = [(V

– (V

- 2V))/R ] * (V

- V

) = [(2V - (V

/R ] * (V

- V

) =

OL_MAX

CCO_MAX

OL_MAX

CCO_MAX

OL_MAX

CCO_MAX

OL_MAX

L

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

873990AY

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REV. B JUNE 13, 2005

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ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

RELIABILITY INFORMATION

TABLE 9. θ_JA^VS. AIR FLOW TABLE FOR 52 LEAD LQFP

θ_JAbyVelocity (Linear Feet per Minute)

0

200

47.1°C/W

36.4°C/W

500

42.0°C/W

34.0°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

58.0°C/W

42.3°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS873990 is: 5788

Pin compatible with the MPC990

873990AY

www.icst.com/products/hiperclocks.html

REV. B JUNE 13, 2005

13

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP

T^ABLE10. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BCC

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

52

--

1.60

0.15

1.45

0.38

0.20

A1

A2

b

0.05

1.35

0.22

0.09

--

1.40

0.32

c

--

D

12.00 BASIC

10.00 BASIC

12.00 BASIC

10.00 BASIC

0.65 BASIC

--

D1

E

E1

e

L

0.45

0.75

θ

--

0°

7°

ccc

--

0.08

Reference Document: JEDEC Publication 95, MS-026

873990AY

www.icst.com/products/hiperclocks.html

REV. B JUNE 13, 2005

14

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

TABLE 11. ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature

ICS873990AY

ICS873990AYT

ICS873990AYLF

ICS873990AYLFT

ICS873990AY

TBD

52 Lead LQFP

tray

0°C to 70°C

52 Lead LQFP

500 tape & reel

tray

52 Lead "Lead-Free" LQFP

TBD

500 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

873990AY

www.icst.com/products/hiperclocks.html

REV. B JUNE 13, 2005

15

ICS873990

LOW VOLTAGE, LVCMOS/

CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR

Integrated

Circuit

Systems, Inc.

REVISION HISTORY SHEET

Description of Change

Rev

Table

Page

Date

1

6

Features Section - added Lead-Free bullet.

Crystal Characteristics - added Drive Level.

B

T5

6/13/05

T11

15

Ordering Information Table - added Lead-Free part number and note.

873990AY

www.icst.com/products/hiperclocks.html

REV. B JUNE 13, 2005

16


型号：	ICS873990AYLFT
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	LOW VOLTAGE, LVCMOS/ CRYSTAL-TO-LVPECL/ECL CLOCK GENERATOR 低电压， LVCMOS / CRYSTAL - TO- LVPECL / ECL时钟发生器晶体时钟发生器外围集成电路
文件：	总16页 (文件大小：158K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS873990AYLFT [ICSI]

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