ICS874005AGT [ICSI]

PCI EXPRESS TM JITTER ATTENUATOR; PCI EXPRESS TM抖动衰减器


型号：	ICS874005AGT
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	PCI EXPRESS TM JITTER ATTENUATOR PCI EXPRESS TM抖动衰减器衰减器 PC
文件：	总12页 (文件大小：188K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

GENERAL DESCRIPTION

FEATURES

The ICS874005 is a high performance Diff- • Five differential LVDS output pairs

ICS

HiPerClockS™

erential-to-LVDS Jitter Attenuator designed for

• One differential clock input

use in PCI Express systems. In some PCI

Express systems, such as those found in

desktop PCs, the PCI Express clocks are

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

generated from a low bandwidth, high phase noise PLL

frequency synthesizer. In these systems, a jitter attenuator

may be required to attenuate high frequency random and

deterministic jitter components from the PLL synthesizer

and from the system board. The ICS874005 has 3 PLL

bandwidth modes: 200kHz, 400kHz, and 800kHz. The

200kHz mode will provide maximum jitter attenuation, but

with higher PLL tracking skew and spread spectrum

modulation from the motherboard synthesizer may be

attenuated.The 400kHz provides an intermediate bandwidth

that can easily track triangular spread profiles, while

providing good jitter attenuation. The 800kHz bandwidth

provides the best tracking skew and will pass most spread

profiles, but the jitter attenuation will not be as good as the

lower bandwidth modes. Because some 2.5Gb serdes have

x20 multipliers while others have than x25 multipliers, the

874005 can be set for 1:1 mode or 5/4 multiplication mode

(i.e. 100MHz input/125MHz output) using the F_SEL pins.

• Output frequency range: 98MHz - 160MHz

• Input frequency range: 98MHz - 128MHz

• VCO range: 490MHz - 640MHz

• Cycle-to-cycle jitter: 30ps (maximum)

• 3.3V operating supply

• 3 bandwidth modes allow the system designer to make

jitter attenuation/tracking skew design trade-offs

• 0°C to 70°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

packages

PLL BANDWIDTH

The ICS874005 uses ICS 3^rdGeneration FemtoClock^TM

PLL technology to achive the lowest possible phase noise.

The device is packaged in a 24 Lead TSSOP package,

making it ideal for use in space constrained applications

such as PCI Express add-in cards.

BW_SEL

0 = PLL Bandwidth: ~200kHz

Float = PLL Bandwidth: ~400kHz (Default)

1 = PLL Bandwidth: ~800kHz

PIN ASSIGNMENT

BLOCK DIAGRAM

Pulldown

OEA

nQB2

nQA1

QA1

QB2

V^DDO

QB1

Pulldown

F_SELA

BW_SEL

QA0

Float

F_SELA

0 = ~200kHz

Float = ~400kHz

V^DDO

nQB1

÷5 (default)

÷4

nQA0

QA1

QA0

nQA0

BW_SEL

V^DDA

QB0

1 = ~800kHz

nQB0

F_SELB

OEB

Pulldown

Pullup

CLK

Phase

Detector

VCO

nQA1

QB0

490 - 640MHz

nCLK

GND

nCLK

F_SELA

V^DD

F_SELB

÷5 (default)

÷4

OEA

CLK

nQB0

QB1

M = ÷5 (fixed)

ICS874005

24-LeadTSSOP

4.40mm x 7.8mm x 0.92mm

package body

nQB1

QB2

G Package

nQB2

Top View

Pulldown

F_SELB

Pulldown

Pullup

OEB

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

TABLE 1. PIN DESCRIPTIONS

Number

1, 24

2, 3

Name

nQB2, QB2

nQA1, QA1

V_DDO

Type

Description

Output

Power

Output

Differential output pair. LVDS interface levels.

Output supply pins.

4, 23

5, 6

QA0, nQA0

nFB_OUT

Differential output pair. LVDS interface levels.

Inverting differential feedback output.

Active HIGH Master Reset. When logic HIGH, the internal dividers are

reset causing the true outputs (nQx) to go low and the inverted outputs

(Qx) to go high. When logic LOW, the internal dividers and the outputs

are enabled. LVCMOS/LVTTL interface levels.

Input

Pulldown

Pullup/

Pulldown

BW_SEL

V_DDA

Input

Power

Input

PLL Bandwidth input. See Table 3B.

Analog supply pin.

Frequency select pin for QAx/nQAx outputs.

LVCMOS/LVTTL interface levels.

F_SELA

V_DD

Pulldown

Pullup

Power

Core supply pin.

Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are

active. When LOW, the QAx/nQAx outputs are in a high impedance

state. LVCMOS/LVTTL interface levels.

OEA

Input

CLK

nCLK

GND

Input

Pulldown Non-inverting differential clock input.

Pullup

Inverting differential clock input.

Power supply ground.

15, 16

Power

Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are

active. When LOW, the QBx/nQBx outputs are in a high impedance

state. LVCMOS/LVTTL interface levels.

OEB

Input

Pullup

Frequency select pin for QBx/nQBx outputs.

LVCMOS/LVTTL interface levels.

F_SELB

Input

Pulldown

19, 20

21, 22

nQB0, QB0

nQB1, QB1

Output

Differential output pair. LVDS interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

C_IN

Input Capacitance

Input Pullup Resistor

kΩ

R_PULLUP

R_PULLDOWNInput Pulldown Resistor

TABLE 3A. OUTPUT ENABLE FUNCTION TABLE

TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL

Inputs

PLL

Inputs

Outputs

Bandwidth

~200kHz

~800kHz

~400kHz

PLL_BW

OEA/OEB QAx/nQAx QBx/nQBx

HiZ

Enabled

Float

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

ABSOLUTE MAXIMUM RATINGS

SupplyVoltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only.Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

Inputs, V

-0.5V to V_DD+ 0.5 V

-0.5V to V_DDO+ 0.5V

70°C/W (0 lfpm)

-65°C to 150°C

Outputs, V_O

PackageThermal Impedance, θ

StorageTemperature, T

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_DD

V_DDA

V_DDO

I_DD

Core Supply Voltage

3.135

3.3

3.465

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

I_DDA

I_DDO

115

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

OEA, OEB, MR,

F_SELA, F_SELB

V_DD+ 0.3

V_IH

Input High Voltage

BW_SEL

_DD- 0.4

-0.3

OEA, OEB, MR,

F_SELA, F_SELB

0.8

V_IL

V_IM

I_IH

Input Low Voltage

Input Mid Voltage

Input High Current

BW_SEL

OEA, OEB

F_SELA, F_SELB

MR, BW_SEL

BW_SEL,

OEA, OEB

MR,

F_SELA, F_SELB

0.4

V_DD/2 + 0.1

V_DD/2 - 0.1

V_DD= V_IN= 3.465V

µA

_DD= V_IN= 3.465V

_DD= 3.465V, V_IN= 0V

V_DD= 3.465V, V_IN= 0V

150

µA

-150

-5

I_IL

Input Low Current

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD=V_DDA=V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

I_IHInput High Current

Test Conditions

Minimum Typical Maximum Units

CLK

_DD= V_IN= 3.465V

V_DD= V_IN= 3.465V

150

µA

nCLK

CLK

150

µA

I_IL

Input Low Current

nCLK

-150

0.15

V_PP

Peak-to-Peak Input Voltage

1.3

V_CMR

Common Mode Input Voltage; NOTE 1, 2

GND + 0.5

V_DD- 0.85

NOTE 1: Common mode voltage is defined as V_IH.

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V_DD+ 0.3V.

TABLE 4D. LVDS DC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

V_OD

Differential Output Voltage

275

375

485

Δ V_OD

V_OS

V_ODMagnitude Change

Offset Voltage

1.2

1.35

1.5

Δ V_OS

V_OSMagnitude Change

TABLE 5. AC CHARACTERISTICS, V_DD= V_DDA= V_DDO= 3.3V 5ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

f_MAX

Output Frequency

160

MHz

tjit(cc)

tsk(o)

t_R/ t_F

odc

Cycle-to-Cycle Jitter, NOTE 1

Output Skew; NOTE 2, 3

Output Rise/Fall Time

Output Duty Cycle

20ꢀ to 80ꢀ

300

550

ꢀ

NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V_DDO/2.

NOTE 3: These parameters are guaranteed by characterization. Not tested in production.

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

PARAMETER MEASUREMENT INFORMATION

V_DD,

V_DDO

V_DDA

V_DD

nCLK

CLK

SCOPE

3.3V 5ꢀ

POWER SUPPLY

Float GND

V_PP

V_CMR

Cross Points

LVDS

–

nQx

GND

3.3V LVDS OUTPUT LOAD ACTEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nQA0, nQA1

nQB0:nQB2

nQx

QA0, QA1

QB0:QB2

➤

tcycle n

tcycle n+1

➤

nQy

tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

tsk(o)

CYCLE-TO-CYCLE JITTER

OUTPUT SKEW

nQA0, nQA1

nQB0:nQB2

80ꢀ

t_F

80ꢀ

QA0, QA1

QB0:QB2

V_SWING

20ꢀ

t_PW

Clock

Outputs

20ꢀ

t_PERIOD

t_R

t_PW

t_PERIOD

odc =

x 100ꢀ

OUTPUT RISE/FALLTIME

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

V_DD

out

➤

out

➤

DC Input

LVDS

DC Input

100

_OD/Δ V_OD

➤

out

V_OS/Δ V_OS

➤

DIFFERENTIAL OUTPUT VOLTAGE SETUP

OFFSETVOLTAGE SETUP

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise.The ICS874005 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL.V_DD, V_DDA, and V_DDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each V_CCApin.

3.3V

V_DD

.01μF

10Ω

V_DDA

.01μF

10μF

FIGURE 1. POWER SUPPLY FILTERING

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in

single ended levels. The reference voltage V_REF = V_DD/2 is the center of the input voltage swing. For example, if the input

generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andV_DD= 3.3V,V_REF should be 1.25V

should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.

VDD

Single Ended Clock Input

CLK

V_REF

nCLK

0.1u

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the

and other differential signals.BothV_SWINGandV_OHmust meet the driver component to confirm the driver termination requirements.

V_PPand V_CMRinput requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS

face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver

the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

Input

LVPECL

nCLK

HiPerClockS

Input

LVHSTL

ICS

HiPerClockS

LVHSTL Driver

FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

ICS HIPERCLOCKS LVHSTL DRIVER

FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

3.3V

125

LVDS_Driver

Zo = 50 Ohm

CLK

100

nCLK

Receiv er

nCLK

HiPerClockS

Input

Zo = 50 Ohm

LVPECL

FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

LVCMOS CONTROL PINS:

LVDS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

All unused LVDS output pairs can be either left floating or

terminated with 100Ω across. If they are left floating, we

recommend that there is no trace attached.

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 4. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

3.3V

LVDS_Driver

100

100 Ohm Differiential Transmission Line

FIGURE 4. TYPICAL LVDS DRIVERT ERMINATION

SCHEMATIC EXAMPLE

Figure 5 shows an example of ICS874005 application sche- decoupling capacitor should be located as close as possible

matic. In this example, the device is operated at V_DD=3.3V.The to the power pin. The input is driven by a 3.3V LVPECL driver.

VDD = 3.3V

VDDO = 3.3V

Zo = 50 Ohm

100

Zo = 50 Ohm

nQB2

nQA1

QA1

VDDO

QA0

nQAO

BW_SEL

VDDA

F_SELA

VDD

QB2

VDDO

QB1

nQB1

QB0

nQB0

F_SELB

OEB

GND

nCLK

CLK

10uF

0.01u

F_SELB

OEB

BW_SEL

F_SELA

OEA

Zo = 50 Ohm

OEA

874005_tssop24

100

Zo = 50 Ohm

nCLK

CLK

LVPECL Driver

(U1:11)

(U1:4) (U1:23)

10uf

.1uf

FIGURE 5. ICS874005 SCHEMATIC EXAMPLE

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874005AG

REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS874005.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS874005 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_DD= 3.3V + 5% = 3.465V, which gives worst case results.

•

Power (core)_MAX= V_{DD_MAX}* (I_{DD_MAX}+ I_{DDA_MAX}) = 3.465V * (85mA + 15mA) = 346.5mW

Power (outputs)_MAX= V_{DDO_MAX}* I_{DDO_MAX}= 3.465V * 115mA = 398.48mW

Total Power_{_MAX}= 346.5mW + 398.48mW = 745mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of

the device. The maximum recommended junction temperature for HiPerClockS^TMdevices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

q_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used.

Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per

Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.745W * 63°C/W = 117°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air

flow, and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θ_JAFOR 24-LEADTSSOP, FORCED CONVECTION

_JAby Velocity (Linear Feet per Minute)

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

70°C/W

63°C/W

60°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

RELIABILITY INFORMATION

TABLE 7. θ_JA^VS. AIR FLOWT ABLE FOR 24 LEAD TSSOP

θ_JAbyVelocity (Linear Feet per Minute)

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

70°C/W

63°C/W

60°C/W

TRANSISTOR COUNT

The transistor count for ICS874005 is: 1206

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP

TABLE 8. PACKAGE DIMENSIONS

Millimeters

Minimum Maximum

SYMBOL

1.20

0.15

1.05

0.30

0.20

7.90

0.05

0.80

0.19

0.09

7.70

6.40 BASIC

0.65 BASIC

4.30

4.50

0.45

0°

0.75

8°

aaa

0.10

Reference Document: JEDEC Publication 95, MO-153

874005AG

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REV.A JANUARY 25, 2006

ICS874005

PCI EXPRESS™

JITTER ATTENUATOR

Integrated

Circuit

Systems, Inc.

TABLE 9.ORDERING INFORMATION

Part/Order Number

ICS874005AG

Marking

ICS874005AG

TBD

Package

Shipping Packaging

Temperature

0°C to 70°C

24 Lead TSSOP

tube

ICS874005AGT

ICS874005AGLF

ICS874005AGLFT

24 Lead TSSOP

2500 tape & reel

tube

24 Lead "Lead-Free" TSSOP

TBD

2500 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS complaint.

The aforementioned trademarks, HiPerClockS and FemtoClock are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

874005AG

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REV.A JANUARY 25, 2006

ICS874005AGT [ICSI]

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