ICS889874 [ICSI]

DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER; 差分至LVPECL缓冲器/除法器


型号：	ICS889874
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	DIFFERENTIAL-TO-LVPECL BUFFER/DIVIDER 差分至LVPECL缓冲器/除法器
文件：	总14页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

GENERAL DESCRIPTION

FEATURES

The ICS889874 is a high speed 1:2 Differential- • 2 LVPECL outputs

ICS

to-LVPECL Buffer/Divider and is a member of

• Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16

HiPerClockS™

the HiPerClockS™family of high performance

clock solutions from ICS. The ICS889874 has

a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider,

• IN, nIN input can accept the following differential input levels:

LVPECL, LVDS, CML

which allows the device to be used as either a 1:2 fanout

buffer or frequency divider. The clock input has internal

termination resistors, allowing it to interface with several

differential signal types while minimizing the number of

required external components. The device is packaged in

a small, 3mm x 3mm VFQFN package, making it ideal for

use on space-constrained boards.

• Output frequency: > 2.5GHz

• Output skew: 5ps (typical)

• Part-to-part skew: TBD

• Additive jitter, RMS: <0.03ps (design target)

• Supply voltage range:(LVPECL), 2.375V to 3.465V

Supply voltage range: (ECL), -3.465V to -2.375V

• -40°C to 85°C ambient operating temperature

• Pin compatible with SY89874U

BLOCK DIAGRAM

PIN ASSIGNMENT

16 15 14 13

V^T

nQ0

nRESET

Enable

VREF_AC

nQ1

nIN

Enable

MUX

nQ0

00 ÷2

01 ÷4

10 ÷8

nQ1

V_T

ICS889874

16-LeadVFQFN

11 ÷16

nIN

3mm x 3mm x 0.95 package body

K Package

Decoder

Top View

V_{REF_AC}

The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

TABLE 1. PIN DESCRIPTIONS

Number

1, 2

Name

Q0, nQ0

Q1, nQ1

S2, S1, S0

Type

Description

Output

Input

Differential output pair. LVPECL / ECL interface levels.

Select pins. LVCMOS/LVTTL interface levels.

No connect.

3, 4

5, 15, 16

Pullup

Unused

Power

7, 14

V_CC

Positive supply pins.

Synchronizing enable/disable pin. When LOW, resets the divider. When

HIGH, unconnected. Input threshold is V_CC/2V. Includes a 37kΩ pull-up

resistor. LVTTL / LVCMOS interface levels.

nRESET

Input

nIN

V_{REF_AC}

V_T

Input

Output

Input

Inverting differential LVPECL clock input.

Reference voltage for AC-coupled applications.

Termination input.

Input

Non-inverting LVPECL differential clock input.

Negative supply pin.

V_EE

Power

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

R_PULLUP

Input Pullup Resistor

KΩ

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

TABLE 3A. CONTROL INPUT FUNCTION TABLE

Inputs

Outputs

nRESET

Selected Source

IN, nIN

Q0, Q1

Disabled; LOW

Enabled

nQ0, nQ1

Disabled; HIGH

Enabled

IN, nIN

NOTE: After nRESET switches, the clock outputs are disabled or enabled following a

falling input clock edge as shown in Figure 1.

nRESET

nIN

Swing

OUT

FIGURE 1. nRESET TIMING DIAGRAM (WHEN S2 = 1)

TABLE 3B. TRUTH TABLE

Inputs

Outputs

nRESET

Reference Clock (pass through)

Reference Clock ÷2

Reference Clock ÷4

Reference Clock ÷8

Reference Clock ÷16

Q = LOW, nQ = HIGH

Clock Disable; (NOTE 1)

Q = LOW, nQ = HIGH

Clock Disable; (NOTE 1)

NOTE 1: Reset/Disable function is asserted on the next clock input

(IN/nIN) high-to-low transition.

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

ABSOLUTE MAXIMUM RATINGS

SupplyVoltage, V_CC

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage

to the device. These ratings are stress specifi-

cations only. Functional operation of product at

these conditions or any conditions beyond those

listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may

affect product reliability.

-0.5V to +4.0V

Inputs, V_I

-0.5V toV_CC+ 0.5 V

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

Input Current IN, nIN

V_TCurrent, I_VT

50mA

100mA

0.5mA

V_{REF_AC}Sink/Source, I_{VREF_AC}

OperatingTemperature Range, TA -40°C to +85°C

StorageTemperature, T_STG-65°C to 150°C

PackageThermal Impedance, θ_JA51.5°C/W (0 lfpm)

(Junction-to-Ambient)

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_CC= 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

3.3

Maximum Units

V_CC

I_EE

Positive Supply Voltage

Power Supply Current

2.375

3.63

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_CC= 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

V_IH

V_IL

I_IH

Input High Voltage

V_CC+ 0.3

0.8

Input Low Voltage

Input High Current

Input Low Current

V_CC= V_IN= 3.63V

-125

µA

I_IL

V_CC= 3.63V, V_IN= 0V

-300

TABLE 4C. DC CHARACTERISTICS, V_CC= 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

R_IN

Differential Input Resistance (IN, nIN)

100

Ω

V_IH

Input High Voltage

Input Low Voltage

Input Voltage Swing

(IN, nIN)

1.2

V_CC

V_CC- 0.15

2.8

V_IL

V_IN

0.15

0.3

V_{DIFF_IN}

I_IN

Differential Input Voltage Swing

Input Current

Bias Voltage

(IN, nIN)

V_{REF_AC}

V_CC- 1.35

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

TABLE 4D. LVPECL DC CHARACTERISTICS, V_CC= 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C

Symbol Parameter Conditions Minimum

Typical

V_CC- 1.005

V_CC- 1.78

Maximum Units

V_OH

V_OL

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Output Voltage Swing

V_OUT

800

V_{DIFF_OUT}Differential Output Voltage Swing

1.60

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CC- 2V.

TABLE 5. AC CHARACTERISTICS, V_CC= 3.3V 10ꢀ OR 2.5V 5ꢀ; TA = -40°C TO 85°C

Symbol Parameter

Maximum Output Frequency

Condition

Minimum Typical Maximum Units

Output Swing ≥ 450mV

÷ 2, ÷4, ÷8, ÷16

GHz

f_MAX

Maximum Input Frequency

Input Swing: < 400mV

Input Swing: ≥ 400mV

725

Propagation Delay, (Differential);

NOTE 1

t_PD

tsk(o)

Output Skew; NOTE 2, 4

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

TBD

Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section

tjit

<0.03

t_RR

t_R/t_F

t_S

Reset Recovery Time

TBD

180

Output Rise/Fall Time

20ꢀ to 80ꢀ

Clock Enable Setup Time EN to IN, nIN

TBD

t_H

Clock Enable Hold Time

EN to IN, nIN

All parameters characterized at ≤ 1GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

PARAMETER MEASUREMENT INFORMATION

V_CC

SCOPE

V_CC

nIN

LVPECL

V_IN

V_IH

Cross Points

nQx

V_EE

V_IL

V_EE

-0.375V to -1.63V

OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nQx

PART 1

nQx

nQy

PART 2

tsk(pp)

tsk(o)

PART-TO-PART SKEW

OUTPUT SKEW

nIN

80ꢀ

t_F

80ꢀ

V_SWING

20ꢀ

Clock

20ꢀ

nQ0, nQ1

Outputs

t_R

Q0, Q1

t_PD

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

nIN

V_IN, V_OUT

V_{DIFF_IN}, V_{DIFF_OUT}

800mV

(typical)

1600mV

(typical)

t_HOLD

nRESET

t_SET-UP

SETUP & HOLD TIME

SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

APPLICATION INFORMATION

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs.The two different layouts mentioned

are recommended only as guidelines.

50Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion. Figures 2A and 2B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs.Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

3.3V

Z_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

FIGURE 2A. LVPECL OUTPUT TERMINATION

FIGURE 2B. LVPECL OUTPUT TERMINATION

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

TERMINATION FOR 2.5V LVPECL OUTPUT

Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the

LVPECL driver.These terminations are equivalent to terminat- termination is shown in Figure 3C.

ing 50Ω to V_CC- 2V. For V_CC= 2.5V, the V_CC- 2V is very close to

2.5V

VCC=2.5V

2.5V

VCC=2.5V

Zo = 50 Ohm

250

Zo = 50 Ohm

2,5V LVPECL

Driv er

2,5V LVPECL

Driv er

62.5

FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE

FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE

2.5V

VCC=2.5V

Zo = 50 Ohm

2,5V LVPECL

Driv er

FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

2.5V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE

The IN /nIN with built-in 50Ω terminations accepts LVDS,

LVPECL, LVHSTL, CML, SSTL and other differential signals.

Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements.Figures 4A to 4D show interface examples for the

by the most common driver types. The input interfaces sug-

gested here are examples only.If the driver is from another ven-

dor, use their termination recommendation. Please consult with

the vendor of the driver component to confirm the driver termi-

HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.

2.5V

3.3V or 2.5V

2.5V

Zo = 50 Ohm

nIN

Receiver

With

Receiver

With

Built-In

50 Ohm

2.5V LVPECL

LVDS

Built-In

50 Ohm

FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER

BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER

2.5V

Zo = 50 Ohm

nIN

Receiver

With

CML - Built-in 50 Ohm Pull-up

CML - Open Collector

Built-In

50 Ohm

FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR

CML DRIVER

BUILT-IN 50Ω DRIVEN BY A CML DRIVER

WITH BUILT-IN 50Ω PULLUP

2.5V

Zo = 50 Ohm

nIN

Receiver With Built-In 50Ω

SSTL

FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER

889874AK

www.icst.com/products/hiperclocks.html

REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

3.3V LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE

The IN /nIN with built-in 50Ω terminations accepts LVDS,

LVPECL, LVHSTL, CML, SSTL and other differential signals.

Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput require-

ments. Figures 5A to 5E show interface examples for the

by the most common driver types. The input interfaces sug-

gested here are examples only. If the driver is from another ven-

dor, use their termination recommendation. Please consult with

the vendor of the driver component to confirm the driver termi-

HiPerClockS IN/nIN input with built-in 50Ω terminations driven nation requirements.

3.3V

Zo = 50 Ohm

nIN

Receiver

With

Receiver

With

Built-In

50 Ohm

LVPECL

LVDS

Built-In

50 Ohm

FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER

BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER

3.3V

Zo = 50 Ohm

nIN

Receiver

With

CML- Open Collector

CML- Built-in 50 Ohm Pull-Up

Built-In

50 Ohm

FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH

IGURE 5C. H

CLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY A CML DRIVER

^WITHBUILT-IN 50Ω PULLUP

WITH

UILT

IN 50Ω DRIVEN BY A CML DRIVER

PEN

COLLECTOR

3.3V

Zo = 50 Ohm

nIN

Receiver

With

SSTL

Built-In

50 Ohm

FIGURE 5E. HIPER

CLOCKS IN/nIN INPUT WITH

BUILT

IN 50Ω DRIVEN BY AN SSTL DRIVER

889874AK

www.icst.com/products/hiperclocks.html

REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

3.3V DIFFERENTIAL

To prevent oscillation and to reduce noise, it is recommended to

have pullup and pulldown connect to true and compliment of the

unused input as shown in Figure 6.

NPUT WITH

UILT-I

50Ω TERMINATION

NUSED

INPUT

ANDLING

3.3V

nIN

Receiver

with

Built-In

50 Ohm

FIGURE 6. UNUSED INPUT HANDLING

2.5V DIFFERENTIAL

To prevent oscillation and to reduce noise, it is recommended to

have pullup and pulldown connect to true and compliment of the

unused input as shown in Figure 7.

NPUT WITH

UILT-I

50Ω TERMINATION

NUSED

INPUT

ANDLING

2.5V

680

nIN

Receiver

with

680

Built-In

50 Ohm

FIGURE 7. UNUSED INPUT HANDLING

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

RELIABILITY INFORMATION

TABLE 7. θ_JA^VS. AIR FLOW TABLE FOR 16 LEAD VFQFN

θ_JA0 Air Flow (Linear Feet per Minute)

Multi-Layer PCB, JEDEC Standard Test Boards

51.5°C/W

TRANSISTOR COUNT

The transistor count for ICS889874 is: 326

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN

T^ABLE8. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

SYMBOL

MINIMUM

MAXIMUM

0.80

1.0

0.05

0.25 Reference

0.18

0.30

0.50 BASIC

N_D

N_E

3.0

0.25

1.25

3.0

0.25

0.30

1.25

0.50

Reference Document: JEDEC Publication 95, MO-220

889874AK

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REV. A MAY 19, 2004

PRELIMINARY

ICS889874

1:2

TO-LVPECL BUFFER/DIVIDER

Integrated

Circuit

Systems, Inc.

DIFFERENTIAL

TABLE 9. ORDERING INFORMATION

Part/Order Number

ICS889874AK

Marking

Package

Count

120 per tube

3500

Temperature

-40°C to 85°C

874A

16 Lead VFQFN

ICS889874AKT

16 Lead VFQFN on Tape and Reel

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

889874AK

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REV. A MAY 19, 2004

ICS889874 [ICSI]

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