ICS90C65 [ICSI]
Dual Voltage Video/Memory Clock Generator; 双电压的视频/内存时钟发生器
| 型号： | ICS90C65 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Dual Voltage Video/Memory Clock Generator |
| 文件： | 总10页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS90C65
Systems, Inc.
Dual Voltage Video/Memory Clock Generator
Introduction
Features
The Integrated Circuit Systems ICS90C65 is a dual clock
generator for VGA applications. It simultaneously generates
two clocks. One clock is for the video memory, and the other
is the video dot clock.
•
Specified for dual voltage operation (VDD=3.3V or 5V),
but operates continuously from 3.0V to 5.25V
Designed to be powered-down for extended battery life
Backward compatibility to the ICS90C64 and ICS90C63
Dual Clock generator for the IBM-compatible Western
Digital Imaging Video Graphics Array (VGA) LSI
devices, and 8514/A chip sets
Integral loop filter components, reduce cost and phase
jitter
•
•
•
The ICS90C65 has been specifically designed to serve the
portable PC market with operation at either 3.3V or 5V with a
comprehensive power-saving shut-down mode.
•
•
This data sheet supplies sales order information, a functional
overview, signal pin details, a block diagram, AC/DC charac-
teristics, timing diagrams, and package mechanical information.
Generates fifteen video clock frequencies (including
25.175 and 28.322 MHz) derived from a 14.318 MHz
system clock reference frequency
•
•
On-chip generation of eight memory clock frequencies
Video clock is selectable among the 15 internally gener-
ated clocks and one external clock
Description
The Integrated Circuit Systems Video Graphics Array Clock
Generator (ICS90C65) is capable of producing different out-
put frequencies under firmware control. The video output
frequency is derived from a 14.318 MHz system clock avail-
able in IBM PC/XT/AT and Personal System/2 computers. It
is designed to work with Western Digital Imaging Video
Graphics Array and 8514/Adevices to optimize video subsys-
tem performance.
•
•
CMOS technology
Available in 20-pin PLCC, SOIC and DIP packages
The video dot clock output may be one of 15 internally-
generated frequencies or one external input. The selection of
the video dot clock frequency is done through four inputs.
•
•
•
•
VSEL0
VSEL1
VSEL2
VSEL3
VSEL0 and VSEL1 are latched by the SELEN signal. VSEL2
and VSEL3 are used as direct inputs to the VCLK selection.
Table 1-1 is the truth table for VCLK selection.
The input and truth table have been designed to allow a direct
connection to one of the many Western Digital Imaging VGA
controllers or 8514/A chip sets.
TheMCLK outputisoneof eightinternally-generatedfrequen-
cies as shown in Table 1-2. The various VCLK and MCLK
frequencies are derived from the 14.318 MHz input frequency.
The VCLKE and MCLKE input can tristate the VCLK and
MCLK outputs to facilitate board level testing.
Note:ICS90C65N (DIP) pin-out is identical to ICS90C65M (SOIC) pin-out.
90C65ARevA111095
ICS90C65
ICS90C65 VGA Interface
When the power-down capabilities are used, the control signal
for PWRDN is normally held in one of a group of latches. If
the power-down function is not to be used, PWRDN must be
tiedtoVDD,otherwisetheinternalpull-down willplace the chip
in the power-down mode.
The ICS90C65 has two system interfaces: System Bus and
VGAController, as well as other programmable inputs. Figure
1 shows how the Integrated Circuit Systems’s VGA Clock
ICS90C65 is connected to a VGA controller. Western Digital
Imaging VGA controllers normally have a status bit that indi-
cates to the VGAcontroller that it is working with a clock chip.
When working with a clock chip the VGA controller changes
two of its clock inputs to outputs. They are
theVCLK1/VCSLD/VCSEL and VCLK2/VCSEL/VCSELH
outputs and they are used to select the required video frequency.
WD90C26
pull-up at reset
and PR15(5)=0
AMD(3)
LATCH
VCS
VCKIN
VCSEL
MCLK
ICS90C65
VSEL0
VSEL1
VSEL2
PWRDN
SD2
SD3
VCLK
MC
SELEN
CLK1
14.318
MHz
Figure 1
2
ICS90C65
System Bus Inputs
User-Definable Inputs
The system bus inputs are:
The user definable inputs are:
•
•
•
CLKI
VSEL0
VSEL1
•
•
•
•
•
EXTCLK
VLCKE, MCLKE
MSELO-2
VSEL2, VSEL3
PWRDN
The ICS90C65 uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clocks. Data lines D2 and D3 are commonly used as
inputs to VSEL0 and VSEL1 for video frequency selection.
EXTCLK is an additional input that may be internally routed
totheVCLK output. This additional inputis usefulfor support-
ing modes that require frequencies not provided by the
ICS90C65 or for use during board test.
Inputs from VGA Controller
The VGA controller input to the ICS90C65 is:
VCLKE and MCLKE are the output enable signals for VCLK
and MCLK. When low the respective output is tristated.
MSEL0-2 are the memory clock (MCLK) select lines. Ta-
ble 1-2 shows how MCLK frequencies areselected. All signals
in this group have internal pull-up resistors.
•
SELEN
The ICS90C65 is programmed to generate different video
clock frequencies using the inputs of VSEL0, VSEL1, VSEL2,
and VSEL3. The signals VSEL2 and VSEL3 may be supplied
by theVGAcontrolleras is thecaseinWesternDigital Imaging
VGA controllers. The inputs VSEL0-1 are latched with the
signal SELEN. The SELEN input should be an active low
pulse. This active low pulse is generated in Western Digital
Imaging VGAcontrollers during I/O writes to internal register
3C2h.
VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select additional VCLK frequencies. See Table 1-1.
VSEL2 and VSEL3 have internal pull-ups.
PWRDN can place the ICS90C65 in a power-down mode
which drops its supply current requirement below 1 microamp.
When placed in this mode, the digital inputs may be either high
orlowor floatingwithout causing an increase in theICS90C65
supply current.
Note:OnlyVSEL0andVSEL1arelatchedwithsignalSELEN.
The PWRDN pin must be low (It has an internal pull-down.)
in order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high by the ICS90C65
when it is in its low power state.
Outputs to VGA Controller
The outputs from the ICS90C65 to the VGA controller are:
•
•
MCLK
VCLK
If CLKI is being driven by an external source, it may be driven
low or high without a power penalty. If CLKI is at an interme-
diate voltage (VSS+0.5 < VIN <VDD-0.5), there will be a small
increase in supply current. If CLKI is driven at 14.318 MHz
while the chip is in power-down, theICS90C65 supply current
will increase to approximately 1.2 mA.
MCLK and VCLK are the two clock outputs to the VGA
controller.
The SELEN (pin 6) may be used to guard against inadvertent
frequency changes during power-down/powerup sequences.
By holding the SELEN low during power-down and power-up
sequences, the ICS90C65 will retain the most recent video
frequency selection.
Analog Filters
The analog filters are integral to the ICS90C65 device. No
external components are required. This feature reduces PC
board space requirements and component costs. Phase-jitter is
reduced as externally-generated noise cannot easily influence
the phase-locked loop filter.
3
ICS90C65
Power Considerations
The ICS90C65 product requires an AVDD supply free of fast
rise time transients. This requirement may be met in several
ways and is highly dependent on the characteristics of the host
system. A VGA adapter card is unique in that it must function
in an unknown environment. +5 volt power quality is depend-
ent not only on the quality of the power supply resident in the
host system, but also on the other cards plugged into the host’s
backplane. Power supply noise ranges from fair to terrible. As
the VGAadapter manufacturer has nocontrolover this, he must
assume the worst. The best solution is to create a clean +5 volts
by deriving it from the +12 volt supply by using a zener diode
and dropping resistor. A 470 Ohm resistor and 5.1 volt Zener
diode are the least costly way to accomplish this. A .047 to .1
microfarad bypass capacitor tied from AVDD to AvSS insures
good high- frequency decoupling of this point.
Laptop and notebook computers have entirely different prob-
lems with power. Typically they have no +12 volt supply;
however, they are much quieter electrically. Because the de-
signer has complete control of the system architecture, he can
place sensitive components and systems such as the RAMDAC
and Dual Video/Memory Clock away from DRAM and other
noise-generating components. Most systems provide power
that is clean enough to allow for jitter-free DualVideo/Memory
Clock performance if the +5 volt supply is decoupled with a
resistor and 22 microfarad Tantalum capacitor. Digital inputs
that are desired to be held at a static logical high level should
not be tied to +5 volts as this may result in excessive current
drain through the ESD protection diode. The internal pull-up
resistors will adequately keep these inputs high.
4
ICS90C65
Pin Descriptions
The following table provides the pin descriptions for the 20-pin ICS90C65 packages.
PIN
NUMBER
PIN
SYMBOL
TYPE
DESCRIPTION
Reference input clock from system.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLKI
IN
IN
IN
IN
IN
IN
IN
IN
IN
-
IN
OUT
IN
IN
-
MSEL2
EXTCLK
VSEL1
VSEL0
SELEN
VSEL2
VSEL3
MSEL0
DVSS
MSEL1
MCLK
PWRDN
MCLKE
AVDD
AVSS
Select input for MCLK selection.
External clock input for an additional frequency.
Control input for VCLK selection.
Control input for VCLK selection.
Strobe for latching VSEL(0,1) (low enable).
Control input for VCLK selection.
Control input for VCLK selection.
Select input for MCLK selection.
Ground for Digital Circuit.
Select input for MCLK selection.
Memory Clock Output.
Power Down Control.
Enable input for MCLK output (high enables output).
Power supply for analog circuit.
Ground for analog circuit.
-
-
NC
No connection.
Enable input for VCLK output (high enables output).
Video Clock Output.
VCLKE
VCLK
DVDD
IN
OUT
-
Power supply for Digital Circuit.
Note:
CLKI, EXTCLK,VSEL0, VSEL1,VSEL2, VSEL3, SELEN, MSEL0, MSEL1, MSEL2, VCLKE, and MCLKE - input pins have
internal pull-up resistors. PWRDN has an internal pull-down resistor.
5
ICS90C65
Absolute Maximum Ratings
Standard Test Conditions
The characteristics below apply for the following standard test
conditions, unless otherwise noted. All voltages are referenced
to VSS (OV Ground). Positive current flows into the refer-
enced pin.
Ambient Temperature
under bias
Storage temperature
Voltage on all inputs and
outputs with respect to VSS
0°C to 70°C
-40°C to 125°C
0.3 to 7 volts
Operating Temperature
range
0°C to 70°C
Note: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress ratingonly andfunctionaloperation of thedevice at these
or anyotherconditions above those indicated in theoperational
sections of the specifications is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may
affect product reliability.
Power supply voltage
3.0 to 5.25 volts
AC Timing Characteristics
The following notes apply to all of the parameters presented in this section:
1. REFCLK = 14.318 MHz
2. TC = 1/FC
3. All units are in nanoseconds (ns).
4. Maximum jitter is within a range of 30 µs after triggering on a 400 MHz scope.
5. Rise and fall time is between 0.8 and 2.0 VDC unless otherwise stated.
6. Output pin loading = 15pF
7. Duty cycle is measured at VDD/2 unless otherwise stated.
SYMBOL
Tpw
Tsu
Thd
PARAMETER
Strobe Pulse Width
Setup Time Data to Strobe
Hold Time Data to Strobe
MIN
STROBE TIMING
MAX
NOTES
20
20
10
-
-
-
MCLK and VCLK TIMINGS @ 5.0V
Tr
Tf
-
-
-
Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
-
-
2
2
0.5
135
20
Duty Cycle 40% min. to
60% max.
%
MHz
ns
-
-
Output Enable to Tristate
(into and out of) time
15
ns
MCLK and VCLK TIMINGS @ 3.3V
Tr
Tf
-
-
-
Rise Time
Fall Time
Frequency Error
Maximum Frequency
Propagation Delay for Pass Through
Frequency
-
-
3
3
.5
110
30
Duty Cycle 40% min. to
60% max.
%
MHz
ns
-
-
Output Enable to Tristate
(into and out of) time
20
ns
6
ICS90C65
DC Characteristics at 5 Volts VDD
SYMBOL
VDD
VIL
VIH
IIH
PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
MIN
4.75
VSS
2.0
-
MAX
5.25
0.8
VDD
10
0.4
-
30
-
8
UNITS
V
CONDITIONS
V
V
VDD = 5V
VDD = 5V
VIN = VCC
µA
V
V
mA
K ohms
pF
VOL
VOH
IDD
RUP
Cin
-
2.4
-
50
-
-
IOL = 8.0 mA
IOH = 8.0 mA
VDD = 5V
VIN = 0.0V
FC = 1 MHz
FC = 1 MHz
VDD=3.3V
Output High Voltage
Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance
Power-down Supply Current
Internal Pull-down Equivalent
Cout
IPN
12
1.0
-
pF
-
µA
K ohms
RDN
20
VIN=VDD=5V
DC Characteristics at 3.3 Volts V
DD
SYMBOL
PARAMETER
Operating Voltage Range
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
MIN
MAX
UNITS
CONDITIONS
VDD
VIL
VIH
IIH
3.0
VSS
2.0
-
3.6
0.8
VDD
10
0.4
-
20
-
8
V
V
V
VDD = 3.3V
VDD = 3.3V
Vin = VDD
µA
V
V
mA
K ohms
pF
VOL
VOH
IDD
RUP
Cin
-
2.4
-
100
-
-
IOL = 3.0 mA
IOH = 3.0 mA
VDD = 3.3V
VIN = 0.0V
FC = 1 MHz
FC = 1 MHz
VDD =3.3V
Output High Voltage
Supply Current
Internal Pull-up Resistors
Input Pin Capacitance
Output Pin Capacitance
Power-down Supply Current
Internal Pull-down Equivalent
Cout
IPN
12
1.0
-
pF
-
µA
K ohms
RDN
50
VIN =VDD =3.3V
7
ICS90C65
ICS90C65 Timing
8
ICS90C65
Table 1-1 VCLK SELECTION
VSEL
VCLK FREQUENCY (MHz)
3
2
1
0
Pattern 951
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
30.0
77.25
EXTCLK
80.0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
31.5
36.0
75.0
50.0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
40.0
50.0
32.0
44.9
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
25.175
28.322
65.0
36.0
Table 1-2 MCLK SELECTION
MSEL
MCLK FREQUENCIES (MHz)
Pattern 951
2
1
0
0
0
0
0
0
0
1
1
0
1
0
1
33.0
49.218
60.0
30.5
1
1
1
1
0
0
1
1
0
1
0
1
41.612
37.5
36.0
44.296
9
ICS90C65
20-Pin DIP Package
20-Pin SOIC Package
PLCC Package
Ordering Information
ICS90C65N or ICS90C65M or ICS90C65V
Example:
ICS XXXX- XXX N
Package Type
N=DIP (Plastic)
M=SOIC
V=PLCC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3-6 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock Device
10
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