ICS9112BM-18T [ICSI]

Zero Delay, Low Skew Buffer; 零延迟，低偏移缓冲器


型号：	ICS9112BM-18T
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Zero Delay, Low Skew Buffer 零延迟，低偏移缓冲器
文件：	总4页 (文件大小：66K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS9112-18

Zero Delay, Low Skew Buffer

Features

Description

The ICS9112-18 is a low jitter, low-skew, high

performance PLL based zero delay buffer for high

speed applications. Based on ICS’s proprietary low

jitter Phase Locked Loop (PLL) techniques, the

device provides eight low skew outputs at speeds

up to 160 MHz at 3.3 V. The ICS9112-18

includes a bank of four outputs running at 1X, and

another four outputs running at 1/2X. In the zero

delay mode, the rising edge of the input clock is

aligned with the rising edges of all eight outputs.

Compared to competitive CMOS devices, the

ICS9112-18 has the lowest jitter of all.

• Packaged in 16 pin narrow SOIC

• Zero input-output delay

• Four 1X outputs plus four half-X outputs

• Output to output skew is less than 250 ps

• Output clocks up to 160 MHz at 3.3 V

• Ability to generate 2X the input

• Full CMOS outputs with 18 mA output drive

capability at TTL levels at 3.3 V

• Spread Smart™ technology works with spread

spectrum clock generators

ICS manufactures the largest variety of clock

generators and buffers, and is the largest clock

supplier in the world.

• Advanced, low power, sub-micron CMOS process

• 3.0 to 5.5 V operating voltage

Block Diagram

FBIN

PLL

CLKA1

CLKA2

CLKA3

CLKA4

CLKIN

Mux

÷ 2

CLKB1

CLKB2

CLKB3

CLKB4

Control

Logic

S2, S1

MDS 9112-18 F

Revision 050400

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

ICS9112-18

Zero Delay, Low Skew Buffer

Pin Assignment

ICS9112-18

16 FBIN

CLKIN

CLKA1

CLKA2

15 CLKA4

14 CLKA3

VDD

GND

12 GND

Feedback Configuration Table

11 CLKB4

CLKB1

CLKB2

Feedback From

Bank A

CLKA1:A4

CLKIN

CLKB1:B4

CLKIN/2

CLKIN

CLKB3

Bank B

2XCLKIN

16 pin narrow (150 mil) SOIC

Output Clock Mode Select Table

Clocks A1-A4

Clocks B1-B4

Internal Generation

PLL Status

Tri-state (high impedance) Tri-state (high impedance)

None

Running

Tri-state (high impedance)

Running

PLL

Buffer Only (no zero delay)

PLL

Off

Running

Pin Descriptions

Number

Name

CLKIN

CLKA1:4

VDD

Type Description

CLocK INput. Connect to input clock source.

CLocK A bank of four outputs.

2, 3, 14, 15

4, 13

Power supply. Connect both pins to same voltage (either 3.3V or 5V).

Connect to ground.

5, 12

GND

6, 7, 10, 11

CLKB1:4

CLocK B bank of four outputs. These are low skew divide by two of bank A.

Select input #2. Selects mode for outputs per table above.

Select input #1. Selects mode for outputs per table above.

FBIN

FeedBack INput. Determines outputs per Feedback Configuration Table above.

Key: I = Input; O = output; P = power supply connection.

External Components

The ICS9112-18 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.1µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND

on pins 13 and 12, as close to the device as possible. A series termination resistor of 33 Wmay be used close

to the pin for each clock output to reduce reflections.

MDS 9112-18 F

Revision 050400

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

ICS9112-18

Zero Delay, Low Skew Buffer

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum Units

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

-0.5

2000

Inputs and Clock Outputs

Electrostatic Discharge

Ambient Operating Temperature

Soldering Temperature

Junction temperature

Referenced to GND

MIL-STD-883

VDD+0.5

°C

Max of 10 seconds

260

150

Storage temperature

-65

DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

Operating Voltage, VDD

3.00

5.50

VDD/2-1

0.8

Input High Voltage, VIH, CLKIN pin only

Input Low Voltage, VIL, CLKIN pin only

Input High Voltage, VIH

VDD/2+1

VDD/2

Input Low Voltage, VIL

Output High Voltage, VOH

IOH=-18 mA

IOL=18 mA

2.4

Output Low Voltage, VOL

0.4

Output High Voltage, VOH, CMOS level

Operating Supply Current, IDD (Note 2)

IOH=-5 mA

VDD-0.4

No Load, S1 = S2 = 1

Each output

±65

Short Circuit Current

Input Capacitance

S2, S1, FBIN

AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)

FBIN to CLKA1, S1=S2=1

0.8 to 2.0V

Input Clock Frequency

160

1.5

MH z

Output Clock Frequency

Output Clock Rise Time, CL=30pF

Output Clock Fall Time, CL=30pF

Output Clock Duty Cycle, VDD=3.3V

Device to Device Skew, equally loaded

Output to Output Skew, equally loaded

Maximum Absolute Jitter

2.0 to 0.8V

At 1.4V

rising edges at VDD/2

700

250

300

Cycle to Cycle Jitter, 30pF loads

66.67 MHz outputs

500

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

2. With CLKIN = 160 MHz, FBIN to CLKA1

Using Spread Spectrum Input Clocks

The ICS9112-18 uses ICS’ Spread Smart technology, allowing it to accurately track (pass through) any

clocks that use spread spectrum techniques.

MDS 9112-18 F

Revision 050400

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

ICS9112-18

Zero Delay, Low Skew Buffer

Package Outline and Package Dimensions

(For current dimensional specifications, see JEDEC Publication No. 95.)

16 pin SOIC narrow

Inches

Min

Millimeters

Symbol

Max

Min

1.35

0.10

0.33

0.19

9.80

3.80

1.27 BSC

5.80

0.25

0.41

Max

0.0532 0.0688

0.0040 0.0098

0.0130 0.0200

0.0075 0.0098

0.3859 0.3937

0.1497 0.1574

.050 BSC

1.75

0.24

0.51

0.24

10.00

4.00

INDEX

AREA

0.2284 0.2440

0.0099 0.0195

0.0160 0.0500

6.20

0.50

1.27

h x 45°

Ordering Information

Part/Order Number

ICS9112BM-18

Marking*

9112BM-18

Shipping packaging

tubes

Package

Temperature

0-70 °C

16 pin SOIC

ICS9112BM-18T

tape and reel

0-70 °C

*Also indicated on the top of the package are the initials ICS in a box.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its

use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is

intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does

not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

MDS 9112-18 F

Revision 050400

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

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