ICS9147-03 [ICSI]

Frequency Generator & Integrated Buffers for 686 Series CPUs; 频率发生器和缓冲器集成了686系列的CPU


型号：	ICS9147-03
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Frequency Generator & Integrated Buffers for 686 Series CPUs 频率发生器和缓冲器集成了686系列的CPU
文件：	总8页 (文件大小：367K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Integrated

Circuit

ICS9147-03

Systems, Inc.

Frequency Generator & Integrated Buffers for 686 Series CPUs

General Description

Features

•

Total of 15 CPU speed clocks:

The ICS9147-03 generates all clocks required for high

speed RISC or CISC microprocessor systems such as Intel

PentiumPro,AMD or Cyrix processors. Four bidirectional I/O

pins (FS0, FS1, FS2, BSEL) are latched at power-on to the

functionality table. The Six BUS clocks can be selected as

either synchronous at 1/2 CPU speed or asynchronous at

32MHz selected by BSEL latched input.The inputs provide

for tristate and test mode conditions to aid in system level

testing.These multiplying factors can be customized for

specific applications. Glitch-free stop clock controls

provided for SDRAM(5:8) and SDRAM (9:12) banks

(STP2#, STP3#).

- Two copies of CPU clock with VDDL (2.5 to 3.3V)

- Twelve (12) SDRAM (3.3v) plus one

CPUH/AGP (3.3V) clocks

•

Six copies of BUS clocks (synchronous with CPU clock/2

or asynchronous 32 MHz)

250ps output skew window for CPU andSDRAM clocks

and 500ps window BUS clocks. CPU clocks to BUS clocks

skew1-4ns(CPUearly)

•

Two copies of Ref. clock @14.31818 MHz (One driven by

VDDLasIOAPIC)

One 48 MHz (3.3 V TTL) for USB support and single 24

MHz.

Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to

allow 2.5V output (or Std. Vdd)

High drive BUS and SDRAM outputs typically provide

greater than 1 V/ns slew rate into 30 pF loads. CPU outputs

typically provide better than 1V/ns slew rate into 20pF

loads while maintaining 50±5% duty cycle. The REF clock

outputs typically provide better than 0.5V/ns slew rates.

Seperate buffer supply pin VDDL allows for nominal 3.3V

voltage or reduced voltage swing (from 2.9 to 2.5V) for

CPUL (1:2) and IOAPIC outputs.

•

3.0V – 3.7V supply range w/2.5V compatible outputs

48-pinSSOPpackage

Block Diagram

Pin Configuration

48-Pin SSOP

Pentium is a trademark of Intel Corporation

9147-03 Rev A 04/25/01

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9147-03

Functionality with (14.31818 MHz input)

CPUL (1:2)

24M

48M

CPUH

SDRAM

(1:12)

BUS (1:6)

(MHz)

Address Select

SDRAM Clock Enable

(MHz)

DIMM

FS2 FS1 FS0

(MHz)

66.8

68.5

Test/2**

Tristate

BSEL=1 BSEL=0 (MHz)

(MHz)

BANK1 BANK2 BANK3

SDRAM SDRAM SDRAM

STP2# STP3#

33.4

27.5

37.5

34.3

(1:4)

(5:8)

(9:12)

Stopped Stopped

Low

Stopped

Low

Stopped

Low

Test/4** Test/3** Test/4** Test/2**

Tristate Tristate Tristate Tristate

**Test: is the frequency applied to the X1 input. Can be crystal or tester generated clock

overriding crystal at X1 pin.

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

REF

FS1

OUT

Reference clock output*

Logic input frequency select Bit1*. Input latched at Poweron.

3, 9, 16, 22,

27, 33, 39, 45

GND

PWR

Ground.

VDDL

BUS (1:5)

BUS6

Crystal input. Nominally 14.318 MHz. Has internal load cap

OUT

PWR

OUT

Crystal output. Has internal load cap and feedack resistor to X1

2.5 or 3.3V buffer power for CPUL and IOAPIC output buffers.

BUS clock outputs. see select table for frequency

8, 10, 11, 12, 14,

BUS clock output. See select table for frequency.*

FS0

Logic input frequency select Bit0.*. Input latched at Poweron.

Bank enable solutions for SDRAM clocks see table above, Clocks are

enabled in groups of 4. (STP2# stops DIMM bank2, STP3# stops DIMM

bank 3 when low).

23, 24

STP# (2:3)

24M

OUT

24MHz fixed clock.*

Logic input* for selecting synchronous or asynchronous BUS frequency-

see table above. Input latched at Poweron.*

BSEL

1, 6, 13, 19,

30, 36, 48

17, 18, 20, 21, 28,

29, 31, 32, 34,

35, 37, 38

VDD3

PWR

OUT

3.3 volt core logic and buffer power

SDRAM (1:12)

SDRAM clocks at CPU speed. See select table for frequency.

CPUH/AGP

CPUL (1:2)

OUT

CPU clock operates at SDRAM VDD level (3.3V nom), for AGP etc.

CPU clock output clocks .See select table for frequency. Operates at

down to 2.5V controlled by VDDL pin.

Pins not internally connected.

48 MHz fixed clock output*.

Logic input frequency select Bit 2*. Input latched at Poweron.

Reference clock (14.318MHz) powered by VDDL,

operating 2.5 to 3.3V.

42, 43

7, 25, 26

N/C

48M

FS2

—

OUT

IOAPIC

OUT

* Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

ICS9147-03

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are

stress specifications only and functional operation of the device at these or any other conditions above those listed in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect product reliability.

Electrical Characteristics at 3.3V

V_DD= 3.0 – 3.7V, T_A= 0 –70°C unless otherwise stated

DC Characteristics

PARAMETER

Input Low Voltage

Input High Voltage

Input Low Current

Input High Current

SYMBOL

TEST CONDITIONS

STP# and latched inputs

MIN

TYP

MAX

UNITS

V_IL

V_IH

I_IL

0.2VDD

STP# and latched inputs

VIN=0V (STP# inputs)

VIN=VDD (STP# inputs)

0.7V_DD

-28.0

-5.0

-10.5

I_IH

5.0

I_OL1

VOL=0.8V; for IOAPIC,

Output Low Current

Output High Current

CPUH, SDRAM, BUS & REF

30.0

(and CPUL at VDDL = 3.0 to 3.7V)

I_OH1

VOH=2.0V; for IOAPIC,

CPUH, SDRAM, BUS & REF

(and CPUL at VDDL = 3.0 to 3.7V)

-26.0

-16

I_OL2

I_OH2

I_OL3

Output Low Current

Output High Current

VOL=0.8V; for fixed 24, 48 CLKs

VOH=2.0V; for fixed 24, 48 CLKs

25.0

-22.0

-14

VOL=0.8V; for CPUL at

Output Low Current

Output High Current

30.0

VDDL = 2.5V

I_OH3

V_OL1

V_OH1

VOH = 1.7V; for CPUL at

VDDL = 2.5V

-12.5

-9.5

IOL = 10mA; -10mA for IOAPIC,

Output Low Voltage

Output High Voltage

CPUH, SDRAM, BUS & REF

0.22

2.8

0.4

(and CPUL at VDDL = 3.0 to 3.7V)

IOH = -10mA;

for CPUH, SDRAM, BUS & REF

(and CPUL at VDDL = 3.0 to 3.7V)

2.4

V_OL2

V_OH2

V_OL3

Output Low Voltage

Output High Voltage

IOL = 8mA; for fixed CLKs

IOH = -8mA; for fixed CLKs

0.25

2.6

0.4

2.4

IOL = 8mA; for CPUL at

Output Low Voltage

0.25

0.4

VDDL = 2.5V

V_OH3

IOH = -8mA; for CPUL at

VDDL = 2.5V

@66.6 MHz; all outputs unloaded

Output High Voltage

Supply Current

1.95

2.1

I_DD

180

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9147-03

Electrical Characteristics at 3.3V

V_DD= 3.0 – 3.7V, T_A= 0 –70°C unless otherwise stated

AC Characteristics

TEST CONDITIONS

20pF load, 0.8 to 2.0V

PARAMETER

Rise Time¹

SYMBOL

MIN

TYP

0.9

0.8

1.5

1.4

1.7

1.2

2.0

1.5

MAX

1.5

1.4

2.5

2.4

2.5

2.0

3.0

2.5

UNITS

T_r1

T_f1

T_r2

T_f2

T_r3

T_f3

T_r4

T_f4

D_t

CPU, SDRAM, BUS & REF

20pF load, 2.0 to 0.8V

CPU, SDRAM, BUS & REF

20pF load, 20% to 80%

CPU, SDRAM, BUS & REF

20pF load, 80% to 20%

CPU, SDRAM, BUS & REF

20pF load, 0.8 to 2.0V

fixed 24 & 48 clocks

Fall Time¹

Rise Time¹

Fall Time¹

Rise Time¹

Fall Time¹

Rise Time¹

Fall Time¹

Duty Cycle¹

20pF load, 2.0 to 0.8V

fixed 24 & 48 clocks

20pF load, 0.4 to 2.0V , CPUL with

VDDL = 2.5V

20pF load, 2.0 to 0.4V, CPUL with

VDDL = 2.5V

20pF load @ VOUT=1.4V

CPU & BUS Clocks; Load=20pF,

SDRAM; Load = 30pF

Jitter, One Sigma¹

Jitter, Absolute¹

T_jis1

150

250

25 MHz, BSEL=1

CPU & BUS Clocks; Load=20pF,

SDRAM; Load = 30pF

T_jab1

-250

FOUT=25 MHz, BSEL=1

Jitter, One Sigma¹

T_jis2

T_jab2

F_i

Fixed CLK; Load=20pF

Jitter, Absolute¹

Fixed CLK; Load=20pF

-5

Input Frequency¹

12.0

14.318

16.0

MHz

Logic Input Capacitance¹

Crystal Oscillator Capacitance¹

Power-on Time¹

C_IN

C_INX

t_on

Logic input pins

X1, X2 pins

From VDD=1.6V to 1st crossing of 66.6

MHz VDD supply ramp < 40ms

CPU to CPU; Load=20pF; @1.4V

(Same VDD)

2.5

4.5

Clock Skew¹

T_sk1

T_sk2

T_sk3

T_SR4

150

300

2.6

250

500

BUS to BUS; Load=20pF; @1.4V

CPU to BUS; Load=20pF; @1.4V

(CPU is early)

SDCPU (@3.3V) to CPU (@2.5V)

(2.5V CPU is late)

250

400

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9147-03

Shared Pin Operation -

Input/Output Pins

Test Mode Operation

The ICS9147-03 includes a production test verification

mode of operation. This requires that the FS2 and FS1 pins

be programmed to a logic high and the FS0 pin be

programmed to a logic low(see Shared Pin Operation

section). In this mode the device will output the following

frequencies.

Pins 2, 15, 46 and 47 on the ICS9147-03 serve as dual

signal functions to the device. During initial power-up,

they act as input pins. The logic level (voltage) that is

present on these pins at this time is read and stored into a

4-bit internal data latch. At the end of Power-On reset, (see

AC characteristics for timing values), the device changes

the mode of operations for these pins to an output function.

In this mode the pins produce the specified buffered

clocks to external loads.

Frequency

REF

REF/2

REF/4

REF2

REF/4

REF/3

REF, IOAPIC

48MHz

24MHz

CPU, SDRAM

To program (load) the internal configuration register for

these pins, a resistor is connected to either theVDD (logic 1)

power supply or the GND (logic 0) voltage potential. A 10

Kilohm(10K) resistor is used to provide both the solid CMOS

programming voltage needed during the power-up

programming period and to provide an insignificant load on

the output clock during the subsequent operating period.

BUS

BSEL=1

BSEL=0

Note: REF is the frequency of either the crystal connected

between the devices X1and X2, or, in the case of a device

being driven by an external reference clock, the frequency

of the reference (or test) clock on the device’s X1 pin.

Figs. 1 and 2 show the recommended means of implementing

this function. In Fig. 1 either one of the resistors is loaded

onto the board (selective stuffing) to configure the device’s

internal logic. Figs. 2a and b provide a single resistor

loading option where either solder spot tabs or a physical

jumper header may be used.

These figures illustrate the optimal PCB physical layout

options. These configuration resistors are of such a large

ohmic value that they do not effect the low impedance clock

signals. The layouts have been optimized to provide as little

impedance transition to the clock signal as possible, as it

passes through the programming resistor pad(s).

Fig. 1

ICS9147-03

Fig. 2a

Fig. 2b

ICS9147-03

Recommended PCB Layout for ICS9147-03

NOTE:

This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of

components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible

to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced

with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the

different Vdd planes.

ICS9147-03

In Millimeters

In Inches

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

MIN

2.41

0.20

0.13

MAX

2.80

0.40

0.34

0.25

MIN

.095

.008

.005

MAX

.110

.016

.0135

.010

INDEX

AREA

SEE VARIATIONS

10.03

7.40

10.68

7.60

.395

.291

.420

.299

hh xx 4455°°

0.635 BASIC

0.025 BASIC

0.38

0.50

0.64

1.02

.015

.020

.025

.040

SEE VARIATIONS

0°

8°

0°

8°

- CC --

VARIATIONS

D mm.

D (inch)

SEATING

PLANE

MIN

15.75

MAX

16.00

MIN

.620

MAX

.630

.10 (.004)

Reference Doc.: JEDEC Publication 95, MO-118

10-0034

300 mil SSOP Package

Ordering Information

ICS9147F-03

Example:

ICS XXXX F - PPP

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS = Standard Device

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9147-03 [ICSI]

相关型号：

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ICS9147-09

ICS9147-12

ICS9147-12

ICS9147-14

ICS9147-16

ICS9147-16

ICS9147-22

ICS9147-22

ICS9147F-01

ICS9147F-01LF

ICS9147F-01T