ICS9148F-12 [ICSI]
Pentium/ProTM System Clock Chip; 奔腾/ ProTM系统时钟芯片
| 型号： | ICS9148F-12 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium/ProTM System Clock Chip |
| 文件： | 总18页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-12
TM
Pentium/Pro System Clock Chip
General Description
Features
CPU outputs are stronger drive for multiple loads per pin
The ICS9148-12 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
(ie CPU and NB on one pin)
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus14.314MHz REF(0:1), USB, PlusSuperI/O
Supports single or dual processor systems
Features include four strong CPU, seven PCI and eight
SDRAM clocks. Two reference outputs are available equal to
the crystal frequency. Stronger drive CPUCLK outputs
typically provide greater than 1 V/ns slew rate into 20pF
loads. This device meets rise and fall requirements with 2
loads per CPU output (ie, one clock to CPU and NB chipset,
one clock to two L2 cache inputs).
I2C serial configuration interface provides output clock
disabling and other functions
MODE input pin selects optional power management
input control pins
Two fixed outputs separately selectable as 24 or 48MHz
Separate 2.5V and 3.3V supply pins
2.5Vor3.3Voutputs:CPU, IOAPIC
3.3Voutputs:SDRAM, PCI, REF, 48/24MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
PWR_DWN# pin allows low power mode by stopping crystal
OSC and PLL stages. For optional power management,
CPU_STOP# can stop CPU (0:3) clocks and PCI_STOP#
will stop PCICLK (0:5) clocks. CPU and IOAPIC output
buffer strength controlled by CPU 3.3_2.5# pin to match
VDDL voltage.
48pin300milSSOPand240milTSSOP
Output enable register
PCICLK outputs typically provide better than 1V/ns slew rate
into 30pF loads while maintaining 50±5% duty cycle. The REF
clock outputs typically provide better than 0.5V/ns slew rates.
for serial port control:
1 = enable
0 = disable
The ICS9148-12 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Pin Configuration
Block Diagram
48-Pin SSOP & TSSOP
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70°C
Crystal (X1, X2) = 14.31818 MHz
CPUCLK, SDRAM PCICLK
SEL
(MHz)
(MHz)
0
1
60
30
66.6
33.3
Pentium is a trademark on Intel Corporation.
9148-12RevF4/1/99
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-12
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
2, 1
REF (0:1)
OUT
Reference clock Output
3, 10, 17, 24,
31, 37, 43
GND
X1
PWR
IN
Ground (common)
4
Crystal or reference input, has internal crystal load cap
Crystal output, has internal load cap and feedback
resistor to X1
5
X2
OUT
6
MODE
VDD2
IN
PWR
OUT
OUT
IN
Input function selection
7, 15
Supply for PCICLK_F, PCICLK (0:5), nominal 3.3V
Free running PCI clock, not affected by PCI_STOP#
PCI clocks
8
PCICLK_F
PCICLK (0:5)
SEL66/60#
SDATA
9, 11, 12, 13, 14, 16
18
19
20
21
22
23
25
Selects 60MHz or 66.6MHz for SDRAM and CPU
I2C data input
IN
SCLK
IN
I2C clock input
VDD4
PWR
OUT
OUT
PWR
OUT
IN
Supply for 48/24MHzA, 48/24MHzB, nominal 3.3V
48/24MHz driver output for USB or Super I/O
48/24MHz driver output for USB or Super I/O
Supply for PLL core, nominal 3.3V
SDRAM clock 60/66.6MHz (selected)
Halts PCI Bus (0:5) at logic "0" level when low
SDRAM clock 60/66.6MHz (selected)
Halts CPU clocks at logic "0" level when low
48/24MHzA
48/24MHzB
VDD
SDRAM7
PCI_STOP#
SDRAM6
CPU_STOP#
26
OUT
IN
27
Supply for SDRAM (0:5), SDRAM6/CPU_STOP#,
SDRAM7/PCI_STOP#, nominal 3.3V
28, 34
VDD3
PWR
40
VDDL2
CPUCLK (0:3)
SDRAM (0:5)
PWR_DWN#
IOAPIC
PWR
OUT
OUT
IN
Supply for CPUCLK (0:3), either 2.5 or 3.3V nominal
CPUCLK clock output, powered by VDDL2
SDRAMs clock at 60 or 66.6MHz (selected)
Powers down chip, active low
42, 41, 39, 38
36, 35, 33, 32, 30, 29
44
45
46
OUT
PWR
IOAPIC clock output, (14.318MHz) powered by VDDL1
Supply for IOAPIC, either 2.5 or 3.3V nominal
VDDL1
3.3 or 2.5 VDD buffer strength selection, has pullup to VDD,
nominal 30K resistor.
47
48
CPU3.3-2.5#
VDD1
IN
PWR
Supply for REF (0:1), X1, X2, nominal 3.3V
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#
VDD4 = 48/24MHzA, 48/24MHzB
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:3)
2
ICS9148-12
Power-On Conditions
SEL 66/60#
MODE
PIN #
38, 39, 41, 42
DESCRIPTION
CPUCLKs
FUNCTION
66.6 MHz - w/serial config enable/disable
36, 35, 33, 32,
30, 29, 27, 26
SDRAM
66.6 MHz - All SDRAM outputs
1
1
16, 14, 13, 12,
11, 9, 8
38, 39, 41, 42
36, 35, 33, 32,
30, 29, 27, 26
PCICLKs
CPUCLKs
SDRAM
33.3 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
0
1
16, 14, 13, 12,
11, 9, 8
PCICLKs
PCI_STOP#
CPU_STOP#
PCICLK_F
CPUCLKs
SDRAM
30 MHz - w/serial config enable/disable
Power Management, PCI (0:5) Clocks
Stopped when low
Power Management, CPU (0:5) Clocks
Stopped when low
33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management
66.6 MHz - CPU Clocks w/external Stop Control and
serial config individual enable/disable.
26
27
8
1
0
38, 39, 41, 42
36, 35, 33, 32,
30, 29
66.6 MHz - SDRAM Clocks w/serial config individual
enable/disable.
16, 14, 13, 12,
11, 9
33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
PCICLKs
Power Management, PCI (0:5) Clocks
Stopped when low
Power Management, CPU (0:5) Clocks
Stopped when low
30 MHz - PCI Clock Free running for Power
Management
60 MHz - CPU Clocks w/external Stop control and
serial config individual enable/disable.
26
PCI_STOP#
CPU_STOP#
PCICLK_F
CPUCLKs
SDRAM
27
8
0
0
38, 39, 41, 42
36, 35, 33, 32,
30, 29
60 MHz - SDRAM Clocks w/serial config individual
enable/disable.
16, 14, 13, 12,
11, 9
30 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
PCICLKs
Example:
a) if MODE = 1, pins 26 and 27 are configured as SDRAM7 and SDRAM6 respectively.
b) if MODE = 0, pins 26 and 27 are configured as PCI_STOP# and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then produced
are on the MODE pin as shown in the table below.
CLOCK
REF (0:1)
IOAPIC 0
48/24 MHz
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
14.31818 MHz
48 MHz
3
ICS9148-12
Technical Pin Function Descriptions
VDD(1,2,3,4)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:1),
PCICLK, 48/24MHzA/B and SDRAM(0:7).
SDRAM(0:7)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing
of the SDRAMs output is controlled by the supply voltage
that is applied to VDD3 of the device, operates at 3.3 volts.
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from Ground
to this level. For the actual guaranteed high and low voltage
levels for the Clocks, please consult the DC parameter table
in this data sheet.
48/24MHzA, B
This is a fixed frequency Clock output that is typically used
to drive Super I/O devices. Outputs A and B are defined as
24 or 48MHz by I2C register (see table).
VDDL1,2
This is the power supplies for the CPUCLK and IOAPCI
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies
will have a voltage swing from Ground to this level. For the
actual Guaranteed high and low voltage levels of these
Clocks, please consult the DC parameter table in this Data
Sheet.
IOAPIC
This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level
swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
REF(0:1)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and
X2.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
X1
PCICLK_F
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. See the data tables for the value of this
capacitor.
ThisOutputisequaltoPCICLK(0:5)andisFREERUNNING,
and will not be stopped by PCI_STP#.
PCICLK (0:5)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the
current PCI specification. They run at 1/2 CPU frequency.
SELECT 66.6/60MHz#
X2
This Input pin controls the frequency of the Clocks at the
CPU, PCICLK and SDRAM output pins. If a logic 1 value
is present on this pin, the 66.6 MHz Clock will be selected.
If a logic 0 is used, the 60MHz frequency will be selected.
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor that is connected to ground. See the Data
Sheet for the value of this capacitor.
MODE
This Input pin is used to select the Input function of the
I/
O pins. An active Low will place the I/O pins in the Input
mode and enable those stop clock functions.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which
are in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks are controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
4
ICS9148-12
Technical Pin Function Descriptions
CPU3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic 0 (ground) will indicate
2.5V operation and a logic 1 will indicate 3.3V operation.
This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms. The
I2C inputs will be Tri-Stated and the device will retain all
programming information. This input pin only valid when
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks. This input pin only valid
when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
5
ICS9148-12
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
6
ICS9148-12
Select Functions
PCI,
PCI_F
24 MHz
Selection
48 MHz
Selection
Functionality
CPU
SDRAM
REF
IOAPIC
Tristate
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
HI - Z
Testmode
TCLK/21
TCLK/41
TCLK/21
TCLK1
TCLK1
TCLK/41
TCLK/21
Notes:
1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default on Bits 7, 6, 5, 4, 1, 0 = 0)
(default on Bits 3, 2 = 1)
Note: PWD = Power-Up Default
BIT
Bit 7
Bit 6
PIN#
-
-
DESCRIPTION
PWD
0
0
Reserved
Must be 0 for normal operation
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
In Spread Spectrum, Controls Spreading
(0=1.8% 1=0.6%)
Bit 5
Bit 4
-
0
0
Bit 3
Bit 2
23
22
48/24 MHz (Frequency Select) 1=48 MHz, 0=24 MHz
48/24 MHz (Frequency Select) 1=48 MHz, 0=24 MHz
1
1
Bit1
Bit0
1
1
0
0
1 - Tri-State
0 - Spread Spectrum Enable
1 - Testmode
Bit 1
Bit 0
-
0
0
0 - Normal operation
7
ICS9148-12
Byte 2: PCICLK Clock Register
Byte 1: CPU, 24/48 MHz Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
23
22
-
PWD
DESCRIPTION
48/24 MHz (Act/Inact)
48/24 MHz (Act/Inact)
Reserved
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
16
14
13
12
11
9
-
Reserved
38
39
41
42
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4: SDRAM Clock Register
Byte 3: SDRAM Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1(Act/Inact)
SDRAM0 (Act/Inact)
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
26
27
29
30
32
33
35
36
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 5: Peripheral Clock Register
Byte6:OptionalRegisterforFuture
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
-
-
1
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
Reserved
45
-
IOAPIC0 (Act/Inact)
Reserved
-
Reserved
1
2
REF1 (Act/Inact)
REF0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Note: PWD = Power-Up Default
Note: PWD = Power-Up Default
8
ICS9148-12
Power Management
Clock Enable Configuration
Other Clocks,
SDRAM,
REF,
IOAPICs,
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK
Crystal
VCOs
48/24 MHz A
48/24 MHz B
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Stopped
Running
Running
Running
Running
Off
Off
Running
Running
Running
Running
Running
Running
Running
Running
Low
33.3/30 MHz
Low
66.6/60 MHz
66.6/60 MHz
33.3/30 MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9148-12PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1
1
1
PCI_STOP#
1 (Enabled)1
1
PWR_DWN#
1 (Normal Operation)3
0 (Power Down)4
3mS
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
9
ICS9148-12
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9148-12. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs.All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-12.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-12. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by theICS9148-12 internally.The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
(Drawing shown on next page.)
10
ICS9148-12
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the ICS9148-12 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power
on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
11
ICS9148-12
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
-100
60
IDD3.3OP CL = 0 pF; Select @ 66M
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
400
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
MHz
pF
CIN
Logic Inputs
5
45
3
CINX
Ttrans
Ts
X1 & X2 pins
27
36
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
mS
ps
TSTAB
3
TCPU-SDRAM1 VT = 1.5 V
TCPU-PCI1 VT = 1.5 V;
200
3.2
500
4.5
1.5
ns
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
MIN
TYP
5
MAX UNITS
IDD2.5OP CL = 0 pF; Select @ 66M
20
mA
Supply Current
Power Down
Supply Current
A
µ
IDD2.5PD CL = 0 pF;
0.21
1.0
Skew1
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
150
2.8
500
4
ps
ns
1
1Guarenteed by design, not 100% tested in production.
12
ICS9148-12
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
FO2
CONDITIONS
MIN
60
TYP
MAX UNITS
Output Frequency
66
20
20
MHz
1
Output Impedance
RDSP2A
VO = VDD*(0.5)
10
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2A
VO = VDD*(0.5)
IOH = -28 mA
IOL = 27 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
V
VOH2A
VOL2A
IOH2A
IOL2A
2.4
2.5
0.35
-52
59
0.4
-48
V
mA
mA
49.3
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
0.95
51
2.85
2.85
55
ns
ns
%
1
tf2 A
1
dt2A
1
tsk2A
VT = 1.5 V
80
250
250
150
+250
ps
ps
ps
ps
1
tjcyc-cyc2A VT = 1.5 V
170
60
1
Jitter
tj1s2A
VT = 1.5 V
VT = 1.5 V
1
tjabs2A
-250
100
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
FO2
CONDITIONS
MIN
60
TYP
MAX UNITS
Output Frequency
66
20
20
MHz
1
Output Impedance
RDSP2B
VO = VDD*(0.5)
10
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2B
VO = VDD*(0.5)
IOH = -8.0 mA
IOL = 21 mA
VOH = 1.8 V
VOL = 0.5 V
10
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
2.1
2.15
0.3
-22
36
0.4
-18
V
mA
mA
33
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.2
0.95
50
1.5
1.3
ns
ns
ns
ps
ps
ps
ps
1
tf2 B
1
dt2B
55
1
tsk2B
VT = 1.25 V
60
250
250
150
+250
1
tjcyc-cyc2B VT = 1.25 V
150
50
1
Jitter
tj1s2B
VT = 1.25 V
VT = 1.25 V
1
tjabs2B
-250
80
1Guarenteed by design, not 100% tested in production.
13
ICS9148-12
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
30
TYP
-
MAX UNITS
Output Frequency
33
55
55
MHz
1
Output Impedance
RDSP1
VO = VDD*(0.5)
12
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VO = VDD*(0.5)
IOH = -14.5 mA
IOL = 9.4 mA
VOH = 2.0 V
12
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
2.7
0.2
0.4
-22
V
-47
47.5
mA
mA
VOL = 0.8 V
17.1
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
51
2
ns
ns
%
ps
ps
ps
1
tf1
2
1
dt1
55
1
tsk1
VT = 1.5 V
100
50
250
150
250
1
Jitter
tj1s1
VT = 1.5 V
1
tjabs1
VT = 1.5 V
-250
120
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
FO3
CONDITIONS
MIN
60
TYP
MAX UNITS
Output Frequency
66
24
24
MHz
1
Output Impedance
RDSP3
VO = VDD*(0.5)
10
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VO = VDD*(0.5)
IOH = -24 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
V
VOH3
VOL3
IOH3
IOL3
2.4
2.5
0.35
-47
0.4
-40
V
mA
mA
41
45
47.5
1
Rise Time
Fall Time
Duty Cycle
Skew
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.45
1.2
51
80
40
-
1.7
1.5
55
ns
ns
%
ps
ps
ps
1
Tf3
1
Dt3
1
Tsk3
VT = 1.5 V
250
150
250
1
Jitter
Tj1s3
VT = 1.5 V
1
Tjabs3
VT = 1.5 V
-250
1Guarenteed by design, not 100% tested in production.
14
ICS9148-12
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
FO4
CONDITIONS
MIN
10
TYP
MAX UNITS
MHz
Output Frequency
14.318
1
Output Impedance
RDSP4A
VO = VDD*(0.5)
30
30
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN4A
VO = VDD*(0.5)
IOH = -13 mA
IOL = 18 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
V
VOH4A
VOL4A
IOH4A
IOL4A
2.5
2.6
0.35
-29
37
0.4
-23
V
mA
mA
33
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr4A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
1.6
51
160
-
2
ns
ns
%
1
tf4 A
2
1
dt4A
45
55
1
tj1s4A
VT = 1.5 V
350
600
ps
pS
1
tjabs4A
VT = 1.5 V
-600
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
FO4
CONDITIONS
MIN
60
TYP
MAX UNITS
Output Frequency
66
30
30
MHz
1
Output Impedance
RDSP4B
VO = VDD*(0.5)
10
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN4B
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
VOH = 1.7 V
VOL = 0.7 V
10
Ω
V
VOH4\B
VOL4B
IOH4B
IOL4B
2.1
2.2
0.25
-17
16
0.3
-15
V
mA
mA
15
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.1
53
130
-
1.6
1.6
60
ns
ns
%
1
tf4 B
1
dt4B
40
1
tj1s4B
VT = 1.25 V
300
700
ps
pS
1
tjabs4B
VT = 1.25 V
-700
1Guarenteed by design, not 100% tested in production.
15
ICS9148-12
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
FO7
CONDITIONS
MIN
TYP
MAX UNITS
MHz
14.318
RDSP7
RDSN7
VOH7
VOL7
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -24 mA
IOL = 23 mA
VOH = 2.0 V
10
10
24
24
Ω
Ω
2.4
2.5
0.35
-47
V
0.4
-40
V
IOH7
mA
mA
IOL7
VOL = 0.8 V
41
47.5
1
Rise Time
Fall Time
Duty Cycle
Jitter
Tr7
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.4
52
150
-
2
2
ns
ns
%
1
Tf7
1
Dt7
45
45
1
Tj1s7
VT = 1.5 V
350
600
ps
pS
1
Tjabs7
VT = 1.5 V
-600
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 24M, 48M, REF(1:2)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Frequency
Output Frequency
SYMBOL
FO24M
CONDITIONS
MIN
20
TYP
24
MAX UNITS
MHz
FO48M
48
MHz
FOREF
14.318
MHz
1
Output Impedance
RDSP5
VO = VDD*(0.5)
60
60
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VO = VDD*(0.5)
IOH = -16 mA
IOL = 9 mA
20
Ω
V
VOH5
VOL5
IOH5
IOL5
2.4
2.5
0.2
-29
25
0.4
-22
V
VOH = 2.0 V
VOL = 0.8 V
mA
mA
16
45
1
Rise Time
Fall Time
Duty Cycle
Jitter
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.7
51
4
ns
ns
%
ps
1
tf5
4
1
dt5
55
1
tj1s5A
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
50
150
350
250
600
1
tj1s5B
150
120
-
1
tjabs5A
-250
-600
1
tjabs5B
ps
1Guarenteed by design, not 100% tested in production.
16
ICS9148-12
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
MAX.
.110
.016
.092
.0135
.0085
MIN.
.620
NOM. MAX.
.625 .630
A
A1
A2
B
AC
48
C
.006
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
See Variations
0°
5°
8°
X
.085
.093
.100
This table in inches
Ordering Information
ICS9148yF-12
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
17
ICS9148-12
240 mil (6.10mm)TSSOP Package
VARIATIONS
COMMON
DIMENSIONS
SYMBOL
N
D
MIN. NOM. MAX.
MIN.
12.40
13.90
NOM.
12.50
14.00
MAX
12.60
14.10
A
A1
A2
b
—
—
—
1.10
0.15
0.95
0.27
0.20
48
56
0.05
0.85
0.17
0.09
0.90
—
C
—
D
E1
e
See Variations
6.00
6.10
0.50 BSC
8.10 BSC
0.60
6.20
Ordering Information
E
ICS9148G-12
L
0.50
0.70
N
α
See Variations
—
Example:
0°
8°
Diminisions are in millimeters
ICS XXXX G - PPP
240TSSOP_AN
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
18
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