ICS9148F-58 [ICSI]
Frequency Generator & Integrated Buffers for PENTIUM/ProTM; 频率发生器和缓冲器集成奔腾/ ProTM
| 型号： | ICS9148F-58 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| 文件： | 总14页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-58
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
General Description
The ICS9148-58 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Features
Generates the following system clocks:
-4CPU(2.5V/3.3V)upto100MHz.
-6PCI(3.3V)@ 33.3MHz
-2AGP(3.3V)@2x PCI
-12SDRAMs(3.3V)@eitherCPUorAGP
-2REF(3.3V)@14.318MHz
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-58
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Skew characteristics:
-CPUCPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPU(early) PCI : 1-4ns
Spread Spectrum 0 to -5% down spread.
Serial I2C interface for Power Management, Frequency
Select, Spread Spectrum.
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0)
Efficient Power management scheme through PCI and CPU
STOPCLOCKS.
Uses external 14.318MHz crystal
48pin300milSSOP.
Block Diagram
Pin Configuration
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
VDD4=AGP(0:1)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
VDDL=CPUCLK(0:3)
9148-58 Rev C 12/07/98
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9148-58
Pin Descriptions
PIN NUMBER
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
1
2
CPU3.3#_2.51,2
IN
PWR
IN
CPU1. Latched input2
3,9,16,22,27,
33,39,45
GND
X1
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
5
X2
OUT
PWR
OUT
6,14
VDD2
PCICLK_F
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchrounous with CPUCLKs with 1-4ns
skew (CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
PCI clock output. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
7
FS11, 2
IN
OUT
IN
PCICLK0
FS21, 2
8
10, 11, 12, 13
15, 47
PCICLK(1:4)
AGP (0:1)
OUT
OUT
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Advanced Graphic Port outputs, powered by VDD4.
This asyncheronous input halts CPUCLK (0:3) and AGP (0:1) clocks at
logic 0 level, when input low (in Mobile Mode, MODE=0)
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
This asyncheronous input halts PCICLK(0:5) clocks at logic 0 level, when
input low (In mobile mode, MODE=0)
CPU_STOP#1
SDRAM 11
PCI_STOP#1
SDRAM 10
IN
17
18
OUT
IN
SDRAM clock output. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
SDRAM clock outputs. Frequency is selected by the SD_SEL latched input.
SD_SEL = 1 at power on causes SDRAM frequency = CPU frenquencies
SD_SEL = 0 at power on causes SDRAM frequencies = AGP frequencies
Supply for SDRAM (0:11), CPU Core and 24, 48MHz clocks,
nominal 3.3V.
OUT
20, 21,28, 29, 31,
32, 34, 35,37,38
SDRAM (0:9)
VDD3
OUT
PWR
19,30,36
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
24MHz
OUT
24MHz output clock, for Super I/O timing.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock, for USB timing.
Frequency select pin. Latched Input Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frequencies.
25
26
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
40, 41, 43, 44
42
CPUCLK(0:3)
VDDL
REF1
OUT
PWR
OUT
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Supply for CPU (0:3), either 2.5V or 3.3V nominal
14.318MHz reference clock.
46
48
Latched input at Power On selects either CPU (SDSEL=1) or AGP
(SD_SEL=0) frequencies for the SDRAM clock outputs.
Supply for AGP (0:1)
SD_SEL
VDD4
IN
PWR
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-58
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
0
SDRAM 11
(OUTPUT)
SDRAM 10
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF,
24/48MHz
AGP,
CPUCLK
Outputs
PCICLK
(0:5)
Crystal
OSC
CPU_STOP# PCI_STOP#
VCO
and SDRAM
0
1
1
1
1
0
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Functionality
VDD1, 2, 3, 4=3.3V±5%,VDDL = 2.5V±5% or 3.3 ±5%, TA= 0 to 70°C
Crystal (X1, X2) = 14.31818MHz
S DRAM (M Hz)
C P U
(M Hz)
F S 2
F S 1
F S 0
P C I (M Hz)
AGP (M Hz)
S D_S EL= 1
S D_S EL=0
66.6
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100.2
95.25
83.3
133.3
75
124
66.8
112
100.2
95.25
83.3
133.3
75
33.3
31.75
33.3
44.3
37.5
41.3
33.4
37.3
66.6
63.5
66.6
88.7
75
82.7
66.8
74.7
63.5
66.6
88.7
75
124
82.7
66.8
112
66.8
74.7
3
ICS9148-58
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C
programming application note.
How to Write:
Send the address D2(H) .
Send two additional dummy bytes, a command code
and byte count.
Send the desired number of data bytes.
See the diagram below:
Clock Generator
Address (7 bits)
+ 8 bits
dummy
command code
+ 8 bits
dummy Byte
count
Data Byte
1
Data Byte
N
ACK
ACK
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
Send the address D3(H).
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
Clock Generator
Address (7 bits)
Byte
Count
Data Byte
1
Data Byte
N
ACK
ACK
ACK
A(6:0) & R/W#
D3(H)
The following specifications should be observed:
1. Operating voltage for I2C pins is 3.3V
2. Maximum data transfer rate (SCLK) is 100K bits/sec.
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister
(default=0)
Bit
Description
PWD
0
Bit 7 Reserved
Bit6 Bit5
CPU Clock
PCI
AGP
Bit4
111
110
101
100
011
010
001
000
100.2
95.25
83.3
133.3
75
33.3
31.75
33.3
44.3
37.5
41.3
33.4
37.3
66.6
63.5
66.6
88.7
75
82.7
66.8
74.7
Note 1. Default at Power-up will be for latched logic inputs
to define frequency. Bits 4, 5, 6 are default to 000,
and if bit 3 is written to a 1 to use Bits 6:4, then
these should be defined to desired frequency at same
write cycle.
Bit
6:4
Note
1
124
66.8
112
Note: PWD = Power-Up Default
0 - Frequency is selected by hardware select,
Bit 3
Latched Inputs
0
1 - Frequency is selected by Bit 6:4 (above)
I2C is a trademark of Philips Corporation
0 - Spread Spectrum center spread type. ±.25%
1 - Spread Spectrum down spread type. 0 to -.5%
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 2
Bit 1
Bit 0
0
0
0
4
ICS9148-58
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
(Reserved)
PCICLK_F (Act/Inact)
AGP0 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
-
40
41
43
44
PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
7
15
14
12
11
10
8
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
1
1
1
1
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
Description
(Reserved)
(Reserved)
(Reserved)
AGP1(Act/Inact)
(Reserved)
(Reserved)
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
5
ICS9148-58
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-58. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-58.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
6
ICS9148-58
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-58. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9148-58 internally.The minimum that the PCICLK (0:5) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
7
ICS9148-58
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
Pins 1 and 2 on the ICS9148-58 serve as dual signal functions
to the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at this
time is read and stored into a 4-bit internal data latch. At the
end of Power-On reset, (see AC characteristics for timing
values), the device changes the mode of operations for these
pins to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
Fig. 1
8
ICS9148-58
Fig. 2a
Fig. 2b
9
ICS9148-58
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; 66.8 MHz
-5
A
µ
IIL2
-200
-100
100
160
320
16
5
IDD3.3OP
mA
Supply Current
CL = 0 pF; 133 MHz
200
Input frequency
Fi
VDD = 3.3 V;
12
27
14.318
MHz
pF
pF
ms
ms
ms
ns
CIN
Logic Inputs
Input Capacitance1
CINX
Ttrans
Ts
X1 & X2 pins
36
45
3
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
2
TSTAB
3
TCPU-PCI VT = 1.5 V; CPU leads
TCPU-SDRAM VT = 1.5 V; Window
1
3
4
Skew1
100
250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
CL = 0 pF; 66.8 MHz
CL = 0 pF;133 MHz
MIN
TYP
10
MAX UNITS
20
IDD2.5OP
mA
40
Supply Current
20
TCPU-PCI VT = 1.5 V; CPU leads
TCPU-SDRAM VT = 1.5 V; Window
1
3
4
ns
ps
Skew1
100
250
1Guaranteed by design, not 100% tested in production.
10
ICS9148-58
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V+/-10%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time
SYMBOL
VOH2A
VOL2A
IOH2A
CONDITIONS
MIN
2.5
TYP MAX UNITS
IOH = -28 mA
IOL = 27 mA
VOH = 2.0 V
VOL = 0.8 V
2.6
0.35
-29
37
V
V
0.4
-23
mA
mA
ns
IOL2A
33
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.1
50
2
1
Fall Time
tf2A
2
ns
1
Duty Cycle
dt2A
55
%
1
Skew
tsk2A
VT = 1.5 V
50
250
150
250
ps
1
Jitter, One Sigma
tj1s2A
VT = 1.5 V
65
ps
1
tjabs2A
VT = 1.5 V
Jitter, Absolute
-250
165
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
tr2B1
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.2
0.3
-20
26
0.4
-16
V
mA
mA
ns
19
40
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.5
1.6
47
1.8
1.8
55
tf2B1
dt2B1
Fall Time
ns
Duty Cycle
%
tsk2B1
Skew
VT = 1.25 V
60
250
ps
Jitter, Single Edge
Displacement2
Jitter, One Sigma
tjsed2B1
tj1s2B1
tjabs2B1
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
200
65
250
150
300
ps
ps
ps
Jitter, Absolute
-300
160
1 Guaranteed by design, not 100% tested in production.
2
Edge displacement of a period relative to a 10-clock-cycle rolling average period.
11
ICS9148-58
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-60
50
0.4
-40
V
mA
mA
ns
IOH1
IOL1
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.6
51
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1a
tj1s1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
150
250
ps
ps
200
tabs1a
tjabs1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-250
-650
135
500
250
650
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.2
-60
50
0.4
-40
V
IOH1
mA
mA
IOL1
41
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Tr1
Tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.5
50
2
2
ns
ns
%
Dt1
55
Tsk1
Tj1s1
Tjabs1
Tjabs1
VT = 1.5 V
200
50
500
150
+250
400
ps
ps
ps
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Absolute1
VT = 1.5 V
VT = 1.5 V (with synchronous PCI)
VT = 1.5 V (with asynchronous PCI)
-250
-400
1Guaranteed by design, not 100% tested in production.
12
ICS9148-58
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
3
VOL1
0.2
-60
50
0.4
-40
V
mA
mA
ns
IOH1
IOL1
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.4 V
1.1
1
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
49
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
VT = 1.5 V
2
3
%
tabs1a
tjabs1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-5
-6
2.5
4.5
5
6
%
%
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz, REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.6
0.3
-32
25
2
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
mA
mA
ns
IOH5
IOL5
16
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
1
Fall Time
tf5
1.9
54
1
ns
1
Duty Cycle
dt5
45
-5
57
3
%
1
Jitter, One Sigma
Jitter, Absolute
tj1s5
VT = 1.5 V
%
1
tjabs5
VT = 1.5 V
-
5
%
1Guaranteed by design, not 100% tested in production.
13
ICS9148-58
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
A
A1
A2
B
AC
.625
.630
48
C
D
See Variations
E
.292
.296
.299
e
H
h
L
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9148F-58
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
14
information being relied upon by the customer is current and accurate.
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