ICS9148F-75-T [ICSI]
Frequency Generator & Integrated Buffers for Mother Boards; 频率发生器和缓冲器集成的主机板
| 型号： | ICS9148F-75-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Mother Boards |
| 文件： | 总17页 (文件大小：642K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9148-75
Integrated
Circuit
Preliminary Product Preview
Systems, Inc.
Frequency Generator & Integrated Buffers for Mother Boards
General Description
Features
The ICS9148-75 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro™,AMD™orCyrix™. Sixteendifferentreference
frequency multiplying factors are externally selectable with
smooth frequency transitions.
•
Generates the following system clocks:
-3CPU(2.5V/3.3V)upto100MHz.
-6PCI(3.3V)@ 33.3MHz(includingonefree
running PCICLK)
-3AGP(3.3V)@2x PCI
-13SDRAMs(3.3V)upto100MHz
-1REF(3.3V)@14.318MHz
-1-48MHz(3.3V)fixed
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-75
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
•
Skew characteristics:
-CPU–CPU<250ps
- CPU(early) – PCI : 1-4ns
-AGP– PCI: 250ps
- PCI – PCI <500ps
•
•
Supports Spread Spectrum modulation & I2C
programming for Power Management, Frequency Select
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection. The
SDRAM12 output may be used as a feed back into an off chip
PLL.
Efficient Power management scheme through power
down PCI,AGPand CPU_STOPclocks.
•
•
Usesexternal14.318MHzcrystal
48pin300milSSOP.
Block Diagram
Pin Configuration
Power Groups
VDD1=REF(0:1),X1,X2
VDD2=PCICLK_F,PCICLK(0:5)
VDD3=SDRAM(0:11), supplyforPLLcore
VDD4=AGP(1:2)
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
VDD5=FixedPLL,48MHz,AGP0
VDDL= CPUCLK(0:3)
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9148-75 Rev C 3/01/00
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9148-75
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
VDD1
REF0
TYPE
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
1
2
FS3
IN
PWR
IN
3,9,16,22,27,
33,39,45
GND
X1
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
5
6
X2
OUT
PWR
OUT
VDD2
PCICLK_F
7
FS11, 2
IN
PCICLK0
FS21, 2
OUT
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
8
10, 11, 12, 13
PCICLK(1:4)
VDD5
BUFFERIN
OUT
PWR
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
14
15
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
CPU_STOP#
SDRAM 11
PCI_STOP#1
SDRAM 10
SDRAM (0:9)
IN
17
18
OUT
IN
OUT
OUT
28, 29, 31, 32, 34,
35,37,38
SDRAM clock outputs.
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
AGP_STOP#1
SDRAM9
PD#1
IN
20
OUT
IN
21
SDRAM8
VDD3
OUT
PWR
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
19,30,36
nominal 3.3V.
23
24
SDATA
SCLK
IN
IN
Data input for I2C serial input.
Clock input of I2C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
AGP0
OUT
25
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port output powered by VDD4.
Supply for AGP (0:2)
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
26
41, 43, 44
40
42
46, 47
48
CPUCLK(0:3)
SDRAM12
VDDL
AGP (1:2)
VDD4
OUT
OUT
PWR
OUT
PWR
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
2
ICS9148-75
Preliminary Product Preview
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
PD#
0
(INPUT)
SDRAM 8
(OUTPUT)
1
Power Management Functionality
PCICLK_F,
REF, 48MHz
and SDRAM
CPUCLK
AGP_STOP# CPU_STOP# PCI_STOP#
Outputs
PCICLK
(0:5)
Crystal
OSC
VCO
AGP(1:2)
1
1
1
0
0
1
1
1
1
1
0
1
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
Running
Running
Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
3
ICS9148-75
Preliminary Product Preview
Functionality
VDD1, 2, 3, 4= 3.3V±5%, TA= 0 to 70°C
Crystal(X1,X2)=14.31818MHz
CPU,SDRAM
(MHZ)
105
REF, IOAPIC
PCI (MHZ) AGP (MHZ) (MHZ)
FS3
1
FS2
1
FS1
1
FS0
1
35
36.67
38.33
40
70
73.34
76.66
80
83.32
86.66
90
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
1
1
1
0
110
1
1
0
1
115
1
1
0
0
120
1
0
1
1
125
41.66
43.33
45
46.67
33.3
31.75
33.3
30
37.5
34.25
33.4
30
1
0
1
0
130
1
0
0
1
135
1
0
0
0
140
93.44
66.6
63.5
66.6
60
0
1
1
1
100
0
1
1
0
95.25
83.3
75
0
1
0
1
0
1
0
0
0
0
1
1
75
75
0
0
1
0
68.5
66.8
60
68.5
66.8
60
0
0
0
1
0
0
0
0
4
ICS9148-75
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
D3(H)
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
5
ICS9148-75
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0:FunctionalityandFrequencySelectRegister(default=0)
Bit
Description
PWD
0
0 - ±0.25% Spread Spectrum Modulation
1 - ±0.6% Spread Spectrum Modulation
Bit (2, 6:4) CPU CLKs PCI CLKs AGP CLKs
Bit 7
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
105
110
115
120
125
130
135
140
100
95.25
83.3
75
35
36.67
38.33
40
41.66
43.33
45
46.67
33.3
31.75
33.3
30
37.5
34.25
33.4
30
70
73.34
76.66
80
83.32
86.66
90
93.44
66.6
63.5
66.6
60
Bit
Note1
(2, 6:4)
75
75
68.5
66.8
60
68.5
66.8
60
0 - Frequency is selected by hardware select,
Bit 3
Latched Inputs
0
1 - Frequency is selected by Bit 6:4 (above)
0 - Normal
Bit 1
Bit 0
0
0
1 - Spread Spectrum Enabled (center spread)
0 - Running
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency;
Bits 2, 6:4 are default to 000
Note: PWD=Power-UpDefault
I2C is a trademark of Philips Corporation
6
ICS9148-75
Preliminary Product Preview
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
(Reserved)
Bit
Pin #
-
-
-
-
40
41
43
44
PWD
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
7
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
15
13
12
11
10
8
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
fromswitching.
1. Inactive means outputs are held LOW and are disabled
fromswitching.
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
25
-
26
-
PWD
Description
AGP0 (Active/Inactive)
(Reserved)
FS0#
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
1
1
-
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
fromswitching.
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Byte 6: Optional Register for Possible
Future Requirements
Bit
Pin #
-
8
7
47
-
2
46
2
PWD
1
-
Description
(Reserved)
FS2#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Pin #
PWD
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
-
FS1#
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
1
1
-
1
1
AGP2 (Act/Inact)
(Reserved)
FS3#
AGP1 (Act/Inact)
REF0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
fromswitching.
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
7
ICS9148-75
Preliminary Product Preview
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9148-75. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9148-75.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
8
ICS9148-75
Preliminary Product Preview
PCI_STOP#Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9148-75. It is used to turn off the PCICLK (0:5) clocks for low power operation.
PCI_STOP#issynchronizedbytheICS9148-75 internally.TheminimumthatthePCICLK(0:5)clocksareenabled(PCI_STOP#
high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
9
ICS9148-75
Preliminary Product Preview
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP (0:1) clocks. for low power
operation.AGP_STOP#issynchronizedbytheICS9148-75.TheAGP2clockisfree-runningandisnotaffectedbyAGP_STOP#.
All other clocks will continue to run while theAGPCLKs are disabled. TheAGPCLKs will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and
AGPCLK off latency is less than 4AGPCLKs. This function is available only with MODE pin latched low.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. AGP_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9148-75.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
5. Only applies if MODE pin latched 0 at power up.
10
ICS9148-75
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9148-75
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
ICS9148-75
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
V
IIH
VIN = VDD
0.1
2.0
5
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
100
IDD3.3OP CL = 0 pF; 66.8 MHz
160
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
14.318
36
MHz
pF
pF
ms
ms
ms
ps
CIN
Logic Inputs
5
45
2
CINX
Ttrans
Ts
X1 & X2 pins
27
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
TSTAB
2
500
6
TCPU-SDRAM1 VT = 1.5 V; SDRAM Leads
TCPU-PCI1 VT = 1.5 V; CPU Leads
-500
2
200
5
ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
CL = 0 pF; 66.8 MHz
MIN
TYP
10
MAX
20
UNITS
mA
Operating
IDD2.5OP
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
-500
2
200
5
500
6
ps
ns
Skew1
1Guaranteed by design, not 100% tested in production.
12
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
2.5
TYP
2.6
0.35
-29
37
MAX
UNITS
V
VOH2A IOH = -28 mA
VOL2A IOL = 27 mA
0.4
-23
V
IOH2A
VOH = 2.0 V
mA
mA
ns
IOL2A
VOL = 0.8 V
33
45
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.1
50
2
1
Fall Time
tf2A
2
ns
1
Duty Cycle
dt2A
55
%
1
Skew
tsk2A
VT = 1.5 V
50
250
150
250
ps
1
Jitter, One Sigma
tj1s2A
VT = 1.5 V
65
ps
1
tjabs2A
VT = 1.5 V
Jitter, Absolute
-250
165
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
VOL1
IOL = 23 mA
0.2
-60
50
0.4
-40
V
IOH1
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.6
50
2
2
1
Fall Time
tf1
ns
1
Duty Cycle
dt1
55
250
%
1
Skew
tsk1
VT = 1.5 V
130
ps
Jitter, One Sigma1
tj1s1a
tj1s1b
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
40
200
135
500
150
250
250
650
ps
ps
ps
ps
Jitter, Absolute1
tabs1a VT = 1.5 V, synchronous
tjabs1b VT = 1.5 V, asynchronous
1Guaranteed by design, not 100% tested in production.
-250
-650
13
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
IOL = 23 mA
0.2
-60
50
0.4
-40
V
VOH = 2.0 V
mA
mA
ns
IOL1
VOL = 0.8 V
41
45
Tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.5
50
2
2
Fall Time1
Duty Cycle1
Tf1
ns
Dt1
55
%
Skew1
Tsk1
VT = 1.5 V
200
50
500
150
+250
400
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Absolute1
Tj1s1
Tjabs1
Tjabs1
VT = 1.5 V
ps
VT = 1.5 V (with synchronous PCI)
VT = 1.5 V (with asynchronous PCI)
-250
-400
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - AGP
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
IOH = -28 mA
MIN
2.4
TYP
3
MAX
UNITS
V
V
VOL1
IOL = 23 mA
0.2
-60
50
1.1
1
0.4
-40
IOH1
VOH = 2.0 V
mA
mA
ns
ns
%
IOL1
VOL = 0.8 V
41
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.4 V
2
2
1
Fall Time
tf1
1
Duty Cycle
dt1
50
130
2
55
250
3
1
Skew
tsk1
VT = 1.5 V
ps
%
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
VT = 1.5 V
tabs1a
VT = 1.5 V, synchronous
VT = 1.5 V, asynchronous
-5
-6
2.5
4.5
5
%
tjabs1b
6
%
1Guaranteed by design, not 100% tested in production.
14
ICS9148-75
Preliminary Product Preview
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH5
CONDITIONS
IOH = -16 mA
MIN
2.4
TYP
2.6
0.3
-32
25
2
MAX
UNITS
V
VOL5
IOL = 9 mA
0.4
-22
V
IOH5
VOH = 2.0 V
mA
mA
ns
IOL5
VOL = 0.8 V
16
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
1
Fall Time
tf5
1.9
50
1
ns
1
Duty Cycle
dt5
45
-5
55
3
%
1
Jitter, One Sigma
tj1s5
VT = 1.5 V
%
1
tjabs5
VT = 1.5 V
Jitter, Absolute
-
5
%
1Guaranteed by design, not 100% tested in production.
15
ICS9148-75
Preliminary Product Preview
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
3 Optional crystal load capacitors are
recommended.
CapacitorValues:
C1, C2 : Crystal load values determined by user
C3:100pFceramic
Allunmarkedcapacitorsare0.01 Fceramic
16
ICS9148-75
Preliminary Product Preview
Ordering Information
ICS9148yF-75-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
17
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