ICS9148YF-60 [ICSI]
Pentium/ProTM System Clock Chip; 奔腾/ ProTM系统时钟芯片
| 型号： | ICS9148YF-60 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium/ProTM System Clock Chip |
| 文件： | 总10页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9148-60
TM
Pentium/Pro System Clock Chip
General Description
Features
The ICS9148-60 is part of a reduced pin count two-chip clock
solution for designs using an Intel BX style chipset.
Companion SDRAM buffers are ICS9179-11 and 12.
Generates system clocks for CPU, PCI, IOAPIC ,
14.314MHz, 48and24MHz.
Supports single or dual processor systems
Skew from CPU (earlier) to PCI clock 1 to 4ns
Separate 2.5V and 3.3V supply pins
2.5Voutputs:CPU, IOAPIC
3.3Voutputs:PCI, REF
No power supply sequence requirements
28 pin SOIC and SSOP
There are two PLLs, with the first PLL capable of spread
spectrum operation. Spread spectrum typically reduces system
EMI by 8-10dB. The second PLL provides support for USB
(48MHz) and 24MHz requirements. CPU frequencies up to
100MHz are supported.
The I2C interface allows stop clock programming, frequency
selection, and spread spectrum operation to be programmed.
Clock outputs include two CPU (2.5V or 3.3V), seven PCI
(3.3V),oneREF(3.3V),oneIOAPIC(2.5Vor3.3V),one48MHz,
and one selectable 48_24MHz.
Spread Spectrum operation optional for PLL1
CPU frequencies to 100MHz are supported.
Pin Configuration
Block Diagram
28 pin SOIC and SSOP
Power Groups
VDD = Supply for PLL core
VDD1=REF0,X1,X2
VDD2=PCICLK_F,PCICLK(0:5)
VDD3=48MHz
VDDL=CPUCLK(0:1)
VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core
GND1=REF0,X1,X2
GND2=PCICLK_F,PCICLK(0:5)
GND3=48MHz
GNDL=CPUCLK(0:1)
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9148-60Rev D10/19/99
information being relied upon by the customer is current and accurate.
ICS9148-60
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap
and feed back resistor from X2
1
X1
IN
2
3
4
X2
GND2
PCICLK_F
PCICLK (0:5)
VDD2
OUT
PWR
OUT
OUT
PWR
PWR
OUT
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Poer for 48MHz
5, 6, 7, 8, 10, 11
6, 9
12
13
VDD3
48MHz
Fixed CLK output @ 48MHz
Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if
pin 27=0 at power up.
Ground for 48MHz
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
Clock input for I2 C input
Data input for I2 C input
Ground for CPUCLK (0:1)
Power for PLL core
CPU and Host clock outputs nominally 2.5V
Power for CPU outputs, nominally 2.5V
IOAPIC clock output 14.318MHz.
Power for IOAPIC
Power for REF outputs.
14.318MHz clock .
Output/Latched input at power up. When low, pin 14 is 48MHz
Ground for REF outputs, X1, X2.
14
15
16
24_48MHz
GND3
OUT
PWR
IN
SEL100/66.6#
17
18
19
20
21, 22
23
24
25
26
SCLK
SDATA
GND
IN
IN
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
IN
VDD
CPUCLK (1:0)
VDDL
IOAPIC
VDDL
VDD1
REF0
SEL48#
GND1
27
28
PWR
2
ICS9148-60
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Dummy Byte Count
Byte 0
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
3
ICS9148-60
Serial Bitmap
Byte3:Functionality&FrequencySelect
& Spread Slect Register
Byte5:
Description
Bit Value = 0 Bit Value = 1
Disabled
Enabled
(low)
Disabled
Enabled
(low)
Bit
Description
0: Center Spread (±0.25)
1: Down Spread (0 to -0.6%)
PWD
Bit Pin# Pin Name PWD
7
0
7
6
4
PCICLK_F
PCICLK5
1
1
Bit
CPU
654
PCI
11
000
001
010
011
100
101
110
111
68.5
75.0
83.3
66.6
103
112
133.3
100
34.25
37.5
41.6
33.3
34.3
37.3
44.43
33.33
Disabled
Enabled
(low)
5
4
3
10
-
PCICLK4
-
1
0
1
6:4
(Reserved)
Disabled
(low)
(Reserved)
0
8
PCICLK3
Enabled
Disabled
(low)
Disabled
(low)
Disabled
(low)
2
1
0
7
6
5
PCICLK2
PCICLK1
PCICLK0
1
1
1
Enabled
Enabled
Enabled
0 - Frequency is selected by
3
2
hardware select SEL100/66.6#
1 - Frequency is selected by 6:4 above
(Reserved)
0
00 - Normal operation
01 - Test mode
10 - Spread sprectrum ON
11 - Tristate all outputs
Notes: 1 = Enabled; 0 = Disabled, outputs held low
10
00
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte4:
Byte6:
Description
Bit Value = 0 Bit Value = 1
Description
Bit Value = 0 Bit Value = 1
Bit Pin# Pin Name PWD
Bit Pin# Pin Name PWD
7
6
-
-
-
-
0
0
(Reserved)
(Reserved)
Disabled
(low)
(Reserved)
(Reserved)
(Reserved)
(Disabled)
(low)
(Reserved)
(Reserved)
7
6
5
4
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disabled
(low)
(Reserved)
(Disabled)
(low)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
5
24
IOAPIC
1
Enabled
4
3
2
-
-
-
-
-
-
0
0
0
(Reserved)
(Reserved)
(Reserved)
2
1
0
21
-
CPUCLK1
-
1
0
1
Enabled
(Reserved)
Enabled
1
0
27
27
REF0
REF0
1
1
Enabled
Enabled
22
CPUCLK0
(Disabled)
(low)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes:
Note: PWD = Power-Up Default
1 = Enabled; 0 = Disabled, outputs held low
For pin 27, there are 2 output stages together for 1 pin. These 2
latches must be both 0 or 1 simultaneously or there will be a short to
ground if one is disabled and the other is running.
4
ICS9148-60
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
Input High Voltage
VIH
VDD+0.3
V
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
VIL
IIH
VSS-0.3
0.8
5
V
VIN = VDD
0.1
2.0
-100
60
A
µ
µ
µ
IIL1
IIL2
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
A
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
170
170
mA
mA
Supply Current
Power Down Supply
Current
66
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
3
650
A
µ
Input frequency
Fi
VDD = 3.3 V;
14.318
MHz
pF
CIN
Logic Inputs
5
45
3
Input Capacitance1
CINX
Ttrans
Ts
X1 & X2 pins
27
1
36
5
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
TSTAB
3
4
TAGP-PCI1 VT = 1.5 V;
3.5
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP66
IDD2.5OP100
CONDITIONS
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
MIN
TYP
16
MAX UNITS
72
mA
mA
Supply Current
Power Down
Supply Current
23
100
IDD2.5PD
CL = 0 pF; With input address to Vdd or GND
10
100
A
µ
tCPU-AGP
tCPU-PCI2
0
1
0.5
2.6
1
4
ns
ns
Skew1
VT = 1.5 V; VTL = 1.25 V
1Guaranteed by design, not 100% tested in production.
5
ICS9148-60
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP MAX UNITS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.2
-41
37
V
V
0.4
-19
mA
mA
ns
IOL2B
19
45
1
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.25
1
1.6
1.6
tr2B
1
Fall Time
ns
tf2B
1
Duty Cycle
48
55
%
dt2B
1
Skew
VT = 1.25 V
30
175
250
150
+250
ps
tsk2B
1
Jitter, Cycle-to-cycle
Jitter, One Sigma
VT = 1.25 V
150
40
ps
tjcyc-cyc2B
1
VT = 1.25 V
ps
tj1s2B
1
Jitter, Absolute
tjabs2B
VT = 1.25 V
-250
140
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V+/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output LowCurrent
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN TYP MAX UNITS
IOH =-11 mA
IOL =9.4 mA
VOH = 2.0 V
VOL =0.8 V
2.4
3.1
0.1
-62
57
V
V
0.4
-22
mA
mA
ns
16
tr1
VOL =0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
50
2
Fall Time1
tf1
2
ns
Duty Cycle1
dt1
45
55
%
Skew1
tsk1
VT = 1.5 V
140
17
500
150
500
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
tjabs1
VT = 1.5 V
ps
VT = 1.5 V
-500
70
ps
1Guaranteed by design, not 100% tested in production.
6
ICS9148-60
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5%; CL = 20 pF
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Jitter, One Sigma1
Jitter, Absolute1
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
2.2
0.33
-41
37
V
V
0.4
-28
mA
mA
ns
IOL4B
29
45
-5
Tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.3
1.6
1.6
55
250
3
Tf4B
Dt4B
1.1
54
60
1
ns
%
ps
%
%
1
VT = 1.25 V
tsk4B
Tj1s4B
VT = 1.25 V
Tjabs4B
VT = 1.25 V
5
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.17
-44
42
V
V
VOL5
0.4
-22
IOH5
mA
mA
IOL5
29
47
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.1
54
1
2
2
ns
ns
%
%
%
dt5
57
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
7
ICS9148-60
Electrical Characteristics - 48, 24 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, One Sigma1
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3
V
V
0.14
-44
42
0.4
-22
mA
mA
ns
IOL5
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.2
4
4
tf5
1.2
52
1
ns
%
%
%
dt5
55
3
tj1s5
tjabs5
VT = 1.5 V
Jitter, Absolute1
VT = 1.5 V
3
5
1Guaranteed by design, not 100% tested in production.
8
ICS9148-60
LEAD COUNT
DIMENSION L
28L
0.704
SOIC Package
Ordering Information
ICS9148yM-60
Example:
ICS XXXX y M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M = SOIC
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
9
ICS9148-60
COMMON
DIMENSIONS
D
VARIATIONS
SYMBOL
MIN.
0.068
0.002
0.066
0.010
0.004
NOM.
0.073
MAX.
0.078
0.008
0.070
0.015
0.008
N
MIN.
0.239
0.239
0.278
0.318
0.397
0.397
NOM.
0.244
0.244
0.284
0.323
0.402
0.402
MAX.
0.249
0.249
0.289
0.328
0.407
0.407
A
A1
A2
b
14
16
20
24
28
30
0.005
0.068
0.012
c
0.006
D
E
See Variations
0.209
0.205
0.212
e
0.0256 BSC
0.307
H
L
0.301
0.025
0.311
0.037
SSOP Package
0.030
N
See Variations
4°
Dimensions in inches
0°
8°
Ordering Information
ICS9148yF-60
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
10
information being relied upon by the customer is current and accurate.
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