ICS9150-02 [ICSI]

Pentium Pro™ and SDRAM Frequency Generator; 高能奔腾™和SDRAM频率发生器


型号：	ICS9150-02
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Pentium Pro™ and SDRAM Frequency Generator 高能奔腾™和SDRAM频率发生器动态存储器
文件：	总8页 (文件大小：513K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS9150-02

Integrated

Circuit

Systems, Inc.

Preliminary Product Preview

Pentium Pro and SDRAM Frequency Generator

General Description

Features

TheICS9150-02 generatesallclocksrequiredforhighspeedRISC

or CISC microprocessor systems such as Intel Pentium Pro. Two

differentreferencefrequencymultiplyingfactorsareexternallyselectable

withsmoothfrequencytransitions. Anoutputenableisprovidedfor

testability.

Generates five processor, six bus, two 14.31818MHz and13

SDRAM clocks.

Synchronous clocks skew matched to 250ps window on

PCLKs and 500ps window on BCLKs

Test clock mode eases system design

SpreadSpectrumavailable

High drive PCICLK & SDRAM outputs typically provide greater

than 1V/ns slew rate into 30pF loads. CPUCLK outputs typically

providebetterthan1V/nsslewrateinto20pFloadswhilemaintaining

I²Cinterfaceforprogramming

Skew from CPU (earlier) to PCI clock -1 to 4ns, center

2.6ns

3.0V 3.7V supply range

56-pin SSOP package

50 5%dutycycle. TheREFclockoutputstypicallyprovidebetter

than0.5V/nsslewrates.

Pin Configuration

Block Diagram

56-Pin SSOP

Functionality

C PU C L K ,

S D R A M

(M H z)

X 1 , R E F

(M H z)

P C IC L K

(M H z)

F S 0

60.0

66.6

14.318

33 .3

Pentium is a trademark of Intel Corporation

PRODUCT PREVIEW documents contain information on new

products in the sampling or preproduction phase of development.

Characteristic data and other specifications are subject to change

without notice.

9150-02 Rev D 09/18/97

ICS9150-02

Preliminary Product Preview

Pin Descriptions

PIN NUMBER

PIN NAME

REF (0:1)

TYPE

DESCRIPTION

2, 3

OUT 14.318 MHz reference clock outputs.

4, 10, 17, 23, 31,

34, 40, 47, 53

GND

PWR Ground.

14.318MHz input. Has internal load cap,(33pF).

Crystal output. Has internal load cap (33pF) and feedback

resistor to X1

OUT

PCICLK_F

PCICLK (0:5)

OUT Free running BUS clock.

OUT BUS clock outputs.

OUT 48MHz clock outputs

9, 11, 12, 13

14, 16

18, 19

48MHz

N/C

Pins are not internally connected.

SDATA

SCLK

Serial data in for serial config port.

Clock input for serial config port.

SEL 66/60#

Logic input for output enable, tristates all outputs when low.

Selects 60MHz or 66MHz for SDRAM and CPU.

1, 7, 15, 20, 26, VDD2, VDD1,

PWR Nominal 3.3V power supply. See power groups for function.

PWR CPU and IOAPIC clock buffer power supply (2.5 - VDD)

37, 43

VDD3, VDD4

50, 56

VDDL2, VDDL1

22, 24, 25, 32, 33,

35, 36, 38, 39, 41, SDRAM (0:12)

42, 44, 45

OUT SDRAM clocks (60/66.6MHz)

54, 55

IOAPIC (1:0)

OUT IOAPIC clock output. (14.31818 MHz) Powered by VDDL1

OUT CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)

46, 48, 49, 51, 52 CPUCLK (0:4)

Power Groups

VDD1 = REF (0:1), X1, X2

VDD2 = PCICLK_F, PCICLK (0:5)

VDD3 = SDRAM (0:12), Supply for PLL core

VDD4 = 48 MHz

VDDL1 = IOAPIC (0:1)

VDDL2 = CPUCLK (0:4)

ICS9150-02

Preliminary Product Preview

Technical Pin Function Descriptions

VDD(1,2,3,4)

IOAPIC(0:1)

Thisisthepowersupplytotheinternalcorelogicofthedeviceaswell

as the clock output buffers for REF(0:1), PCICLK, 48MHz (0:1)

andSDRAM(0:7).

These Outputs are fixed frequency Output Clocks that run at the

ReferenceInput(typically14.31818MHz). Itsvoltagelevelswing

is controlled by VDDL1 and may operate at 2.5 or 3.3volts.

Thispinoperatesat3.3Vvolts. Clocksfromthelistedbuffersthatit

supplieswillhaveavoltageswingfromGroundtothislevel. Forthe

actualguaranteedhighandlowvoltagelevelsfortheClocks,please

consult theDCparameter tableinthis datasheet.

REF (0:1)

The REF Output is a fixed frequency Clock that runs at the same

frequencyastheInputReferenceClockX1ortheCrystal(typically

14.31818MHz) attached across X1 and X2.

VDDL1,2

PCICLK_F

This is the power supplies for the CPUCLK and IOAPCI output

buffers. Thevoltagelevelfortheseoutputsmaybe2.5or3.3volts.

Clocksfromthebuffersthateachsupplieswillhaveavoltageswing

fromGroundtothislevel. FortheactualGuaranteedhighandlow

voltage levels of these Clocks, please consult the DC parameter

tableinthisDataSheet.

This Output is equal to PCICLK(0:5).

PCICLK(0:5)

TheseOutputClocksgenerateallthePCItimingrequirementsfora

Pentium/Pro based system. They conform to the current PCI

specification.Theyrunat1/2CPUfrequency.

GND

FS0

Thisisthepowersupplyground(commonornegative)returnpinfor

theinternalcorelogicandalltheoutputbuffers.

This Input pin controls the frequency of the Clocks at the CPU,

PCICLKandSDRAMoutputpins. Ifalogic1valueispresenton

thispin, the66.6MHzClockwillbeselected. Ifalogic0isused,

the60MHzfrequencywillbeselected.

Thisinputpinservesoneoftwofunctions. Whenthedeviceisused

withaCrystal, X1actsastheinputpinforthereferencesignalthat

comes from the discrete crystal. When the device is driven by an

external clock signal, X1 is the device input pin for that reference

clock. ThispinalsoimplementsaninternalCrystalloadingcapacitor

that is connected to ground. With a nominal value of 33pF no

external load cap is needed for a C_L=17 to 18pF crystal.

I²C

The SDATAand SCLOCK Inputs are use to program the device.

The clock generator is a slave-receiver device in the I²Cprotocol.

It will allow read-back of the registers. See configuration map for

registerfunctions. TheI²CspecificationinPhilipsI²CPeripherals

Data Handbook (1996) should be followed.

48MHz

This Output pin is used only when the device uses a Crystal as the

reference frequency source. In this mode of operation, X2 is an

outputsignalthatdrives(orexcites)thediscreteCrystal. TheX2pin

willalsoimplementaninternalCrystalloadingcapacitornominally

33pF.

ThisisafixedfrequencyclockthatistypicallyusedtodriveSuper

I/O peripheral device needs and USB.

Output Enable tristates the outputs when held low. This pin will

overridetheI²CByte0function, sothattheoutputswillbetristated

whentheOEislowregardlessoftheI²Cdefinedfunction.WhenOE

ishigh, theI²Cfunctionisin activecontrol.

CPUCLK(0:4)

These Output pins are the Clock Outputs that drive processor and

other CPU related circuitry that requires clocks which are in tight

skew tolerance with the CPU clock. The voltage swing of these

ClocksarecontrolledbytheVoltagelevelappliedtotheVDDL2pin

of the device. See the FunctionalityTable for a list of the specific

frequencies that are available for these Clocks and the selection

codes to produce them.

SDRAM(0:12)

TheseOutputClocksareusetodriveDynamicRAMsandarelow

skew copies of the CPU Clocks. The voltage swing of the

SDRAMsoutputiscontrolledbythesupplyvoltagethatisapplied

to VDD3 of the device, operates at 3.3 volts.

ICS9150-02

Preliminary Product Preview

General I²C serial interface information

For the clock generator to be addressed by an I²C controller, the following address must be sent as a start sequence,

with an acknowledge bit between each byte.

Clock Generator

Address (7 bits)

Then Byte 0, 1, 2, etc in

sequence until STOP.

+ 8 bits dummy

command code

+ 8 bits dummy

Byte count

ACK

A(6:0) & R/W#

D2^(H)

The clock generator is a slave/receiver I²C component. It can "read back "(in Philips I²C protocol) the data stored in the

latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB

PIIX4 protocol.

Clock Generator

Address (7 bits)

Byte 0

ACK

Byte 1

ACK

Byte 0, 1, 2, etc in sequence until STOP.

A(6:0) & R/W#

D3^(H)

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I²C interface, the protocol is set to use only block writes from the controller. The bytes

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has

been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two

bytes. The data is loaded until a Stop sequence is issued.

In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

maintain all prior programming information.

At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default

to a 1 (Enabled output state)

Serial Configuration Command Bitmaps

Byte 0: Functional and Frequency Select Clock Register (default = 0)

BIT

Bit 7

Bit 6

PIN#

DESCRIPTION

PWD

Reserved

Must be 0 for normal operation

Bit 5

Bit 4

In Spread Spectrum, Controls type

(0=centered, 1=down spread)

Must be 0 for normal operation

In Spread Spectrum, Controls Controls

Spreading %(0=1.5%, 1=0.5%)

Reserved

Bit 3

Bit 2

Reserved

Bit 1

Bit 0

Bit1

Bit0

1 - Tri-State

Note: PWD = Power-Up Default

0 - Spread Spectrum Enable

1 - Testmode

0 - Normal operation

I²C is a trademark of Philips Corporation

ICS9150-02

Preliminary Product Preview

Select Functions

FUNCTION

OUTPUTS

SDRAM

PCI,

PCI_F

DESCRIPTION

CPU

REF

IOAPIC

Tri - State

Test Mode

Hi-Z

TCLK/2¹

Hi-Z

TCLK/4¹

Hi-Z

TCLK/2¹

Hi-Z

TCLK¹

Hi-Z

TCLK¹

Notes:

1. REF is a test clock on the X1 inputs during test mode.

Byte 1: CPU Clock Register

Byte 2: PCICLK Clock Register

BIT PIN# PWD

DESCRIPTION

Reserved

BIT PIN# PWD

DESCRIPTION

Reserved

Bit 7

Bit 6

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PCICLK_F (Act/Inact)

PCICLK5 (Act/Inact)

PCICLK4 (Act/Inact)

PCICLK3 (Act/Inact)

PCICLK2 (Act/Inact)

PCICLK1 (Act/Inact)

PCICLK0 (Act/Inact)

Reserved

Bit 5 16

Bit 4 14

Bit 3 13

Bit 2 12

Bit 1 11

Reserved

CPUCLK4 (Act/Inact)

CPUCLK3 (Act/Inact)

CPUCLK2 (Act/Inact)

CPUCLK1 (Act/Inact)

CPUCLK0 (Act/Inact)

Bit 0

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Byte 4: SDRAM Clock Register

Byte 3: SDRAM Clock Register

BIT PIN# PWD

DESCRIPTION

SDRAM7 (Act/Inact)

SDRAM6 (Act/Inact)

SDRAM5 (Act/Inact)

SDRAM4 (Act/Inact)

SDRAM3 (Act/Inact)

SDRAM2 (Act/Inact)

SDRAM1 (Act/Inact)

SDRAM0 (Act/Inact)

BIT PIN# PWD

DESCRIPTION

48 MHz0 (Act/Inact)

48 MHz1 (Act/Inact)

Reserved

Bit 7 35

Bit 6 36

Bit 5 38

Bit 4 39

Bit 3 41

Bit 2 42

Bit 1 44

Bit 0 45

Bit 7 18

Bit 6 19

Bit 5

Bit 4 22

Bit 3 24

Bit 2 25

Bit 1 32

Bit 0 33

SDRAM12 (Act/Inact)

SDRAM11 (Act/Inact)

SDRAM10 (Act/Inact)

SDRAM9 (Act/Inact)

SDRAM8 (Act/Inact)

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Byte 6: Peripheral Clock Register

BIT PIN# PWD DESCRIPTION

Byte 5: Peripheral Clock Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

BIT PIN# PWD

DESCRIPTION

Reserved

Bit 7

Bit 6

REF0 (Act/Inact)

IOAPIC1 (Act/Inact)

IOAPIC0 (Act/Inact)

Reserved

Bit 5 54

Bit 4 55

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

REF1 (Act/Inact)

Notes:

1. Byte 6 is reserved by Integrated Circuit Systems for

future applications.

Notes: 1 = Enabled; 0 = Disabled, outputs held low

ICS9150-02

Preliminary Product Preview

Absolute Maximum Ratings

SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V_DD+0.5 V

Ambient OperatingTemperature . . . . . . . . . . . . . . . 0°C to +70°C

StorageTemperature. . . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethoselistedintheoperationalsectionsofthe

specificationsisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproductreliability.

Electrical Characteristics at 3.3V

V_DD= 3.0 3.7V, T_A= 0 70°C unless otherwise stated

DC Characteristics

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9150-02

Preliminary Product Preview

Electrical Characteristics at 3.3V

V_DD= 3.0 3.7V, T_A= 0 70°C unless otherwise stated

AC Characteristics

TEST CONDITIONS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

ICS9150-02

Preliminary Product Preview

SSOP Package

SYMBOL

COMMON DIMENSIONS

VARIATIONS

MIN.

.095

.008

.088

.008

.005

NOM.

.101

.012

.090

.010

MAX.

MIN.

.620

.720

NOM. MAX.

.110

.016

.092

.0135

.010

.625

.725

.630

.730

See Variations

.292

.296

.299

0.025 BSC

.406

.013

.400

.010

.024

.410

.016

.040

.032

See Variations

5°

0°

8°

.085

.093

.100

Ordering Information

ICS9150F-02

Example:

ICS XXXX F - PPP

Pattern Number (2 or 3 digit number for parts with ROM code patterns)

Package Type

F=SSOP

Device Type (consists of 3 or 4 digit numbers)

Prefix

ICS, AV = Standard Device

PRODUCT PREVIEW documents contain information on new

products in the sampling or preproduction phase of development.

Characteristic data and other specifications are subject to change

without notice.

ICS9150-02 [ICSI]

相关型号：

ICS9150-04

ICS9150-04

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ICS9150F-01

ICS9150F-02

ICS9150F-02LF

ICS9150F-04

ICS9150F-04LF

ICS9150F-08

ICS9150F-08LF

ICS9150F-11

ICS9150F-11LF