ICS9150F-01 [ICSI]
Pentium Pro⑩ and SDRAM Frequency Generator; 高能奔腾™和SDRAM频率发生器
| 型号： | ICS9150F-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium Pro⑩ and SDRAM Frequency Generator |
| 文件： | 总14页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9150-01
Systems, Inc.
Pentium Pro™ and SDRAM Frequency Generator
General Description
Features
•
•
Generates five processor, six bus, one 14.31818MHz
The ICS9150-01 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro. Two different reference frequency multiplying
factors are externally selectable with smooth frequency
transitions. An output enable is provided for testability.
and 16 SDRAM clocks.
Synchronous clocks skew matched to 250 ps window
on PCLKs and 500ps window on BCLKs
Test clock mode eases system design
Selectable multiplying ratios
•
•
•
•
Custom configurations available
Output frequency ranges to 100 MHz (depending on
option)
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into
•
•
•
•
3.0V – 3.7V supply range
±
20pF loads while maintaining 50 5% duty cycle. The REF
PC serial configuration interface
Power Management Control Input pins
56-pin SSOP package
clock outputs typically provide better than 0.5V/ns slew rates.
Pin Configuration
Block Diagram
56-Pin SSOP
Functionality
CPUCLK,
X1, REF
(MHz)
PCICLK
(MHz)
FS0
SDRAM
(MHz)
0
1
60.0
66.6
14.318
14.318
30
33.3
Pentium is a trademark of Intel Corporation
9150-01RevE4/25/01
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9150-01
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
3
REF0
OUT 14.318 MHz reference clock outputs.
4, 10, 17, 23, 31,
GND
PWR Ground.
34, 40, 47, 53
5
6
X1
X2
IN
14.318MHz input. Has internal load cap.
OUT Crystal output. Has internal load cap and feedback resistor to X1
Mode select pin for enabling power management features,
29
MODE
IN
has pullup.
8
PCICLK_F
PCICLK (0:5)
OUT Free running BUS clock during PCI_STOP#=0.
9, 11, 12, 13
14, 16
OUT BUS clock outputs.
Select pin for enabling 66.6 MHz or 60 MHz. CPU/SDRAM clock
30
FS0
IN
frequency
27
28
SDATA
SCLK
IN
IN
Serial data in for serial config port.
Clock input for serial config port.
1, 7, 15, 20, 26, VDD2, VDD1,
PWR Nominal 3.3V power supply, see power groups for function.
37, 43
50, 56
VDD, VDD3
CPU and IOAPIC clock buffer power supply, either 2.5 or 3.3V
VDDL2, VDDL1
PWR
nominal.
18, 19, 21, 22, 24,
25, 32, 33, 35, 36, SDRAM (0:11)
38, 39, 41, 42, 44, (14:15)
45
OUT SDRAM clocks (60/66.6MHz)
2, 54, 55
IOAPIC (0:2)
OUT IOAPIC clock output. (14.31818 MHz) Poweredby VDDL1
OUT CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
OUT SDRAM clock (60/66.6 MHz)
IN
OUT SDRAM clock (60/66.6 MHz)
IN Halts PCICLK (0:5) at logic "0" level when low.
46, 48, 49, 51, 52 CPUCLK (0:4)
SDRAM13
32
CPU_STOP#
Halts CPUCLK clocks at logic "0" level when low.
SDRAM12
33
PCI_STOP#
Power Groups
VDD = Supply for PLL core
VDD1 = REF 0, X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:11) (14:15), SDRAM13/CPU_STOP#, SDRAM12/PCI_STOP#
VDDL1 = IOAPIC (0:2)
VDDL2 = CPUCLK (0:4)
2
ICS9150-01
Power-On Conditions
SEL 66/60#
MODE
PIN #
52, 51, 49, 48, 46
DESCRIPTION
CPUCLKs
FUNCTION
66.6 MHz - w/serial config enable/disable
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 33, 32, 25,
24
SDRAM
66.6 MHz - All SDRAM outputs
1
1
9, 11, 12, 13, 14,
PCICLKs
CPUCLKs
33.3 MHz - w/serial config enable/disable
60 MHz - w/serial config enable/disable
16, 8
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 33, 32, 25,
24
SDRAM
60 MHz - w/serial config enable/disable
0
1
1
9, 11, 12, 13, 14,
PCICLKs
CPUCLKs
30 MHz - w/serial config enable/disable
66.6 MHz - w/serial config enable/disable
16, 8
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 25, 24
SDRAM
66.6 MHz - All SDRAM outputs
0
0
33
32
PCI_STOP#
CPU_STOP#
CPUCLKs
Power Management, PCI (0:5) clocks stopped when low
Power Managemen, CPU clocks stopped when low
60 MHz - w/serial config enable/disable
52, 51, 49, 48, 46
45, 44, 42, 41, 39,
38, 36, 35, 22, 21,
19, 18, 25, 24
SDRAM
60 MHz - w/serial config enable/disable
0
33
32
PCI_STOP#
CPU_STOP#
Power Management, PCI (0:5) clocks stopped when low
Power Managemen, CPU clocks stopped when low
Example:
a) if MODE = 1, pins 33 and 32 are configured as SDRAM12, and SDRAM13 respectively.
b) if MODE = 0, pins 33 and 32 are configured as PCI_STOP#, and CPU_STOP# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.
CLOCK
REF 0
IOAPIC (0:2)
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
14.31818 MHz
3
ICS9150-01
Technical Pin Function Descriptions
VDD(1,2,3)
REF0
Thisisthepowersupplytotheinternalcorelogicofthedeviceaswell
as the clock output buffers for REF(0:1), PCICLK, and
SDRAM(0:7).
The REF Output is a fixed frequency Clock that runs at the same
frequencyastheInputReferenceClockX1ortheCrystal(typically
14.31818MHz) attached across X1 and X2.
Thispinoperatesat3.3Vvolts. Clocksfromthelistedbuffersthatit
supplieswillhaveavoltageswingfromGroundtothislevel. Forthe
actualguaranteedhighandlowvoltagelevelsfortheClocks,please
consult the DC parameter table in this data sheet.
PCICLK_F
This Output is equal to PCICLK(0:5) and is FREE RUNNING, and
will not be stopped by PCI_STP#.
PCICLK(0:5)
VDDL1,2
These Output Clocks generate all the PCI timing requirements for a
Pentium/Pro based system. They conform to the current PCI
specification.Theyrunat1/2CPUfrequency.
This is the power supplies for the CPUCLK and IOAPCI output
buffers. Thevoltagelevelfortheseoutputsmaybe2.5or3.3volts.
Clocksfromthebuffersthateachsupplieswillhaveavoltageswing
fromGroundtothislevel. FortheactualGuaranteedhighandlow
voltage levels of these Clocks, please consult the DC parameter
tableinthisDataSheet.
FS0
This Input pin controls the frequency of the Clocks at the CPU,
PCICLK and SDRAM output pins. If a logic “1” value is present on
this pin, the 66.6 MHz Clock will be selected. If a logic “0” is used,
the60MHzfrequencywillbeselected.(ThisisthePowerManagement
Mode)
GND
Thisisthepowersupplyground(commonornegative)returnpinfor
theinternalcorelogicandalltheoutputbuffers.
MODE
X1
This Input pin is used to select the Input function of the I/O pins.
An active Low will place the I/O pins in the Input mode and enable
thosestopclockfunctions. (ThisisthePowerManagementMode)
Thisinputpinservesoneoftwofunctions. Whenthedeviceisused
withaCrystal, X1actsastheinputpinforthereferencesignalthat
comes from the discrete crystal. When the device is driven by an
external clock signal, X1 is the device input pin for that reference
clock. ThispinalsoimplementsaninternalCrystalloadingcapacitor
thatisconnectedtoground. Seethedatatablesforthevalueofthis
capacitor.
CPU_STOP#
ThisisasynchronousactiveLowInputpinusedtostoptheCPUCLK
clocks in an active low state. All other Clocks including SDRAM
clocks will continue to run while this function is enabled. The
CPUCLK’swillhaveaturnONlatencyofatleast3CPUclocks.This
inputpinonlyvalidwhenMODE=0(PowerManagementMode)
X2
This Output pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2 is an
outputsignalthatdrives(orexcites)thediscreteCrystal. TheX2pin
will also implement an internal Crystal loading capacitor that is
connected to ground. See the Data Sheet for the value of this
capacitor.
PCI_STOP#
ThisisasynchronousactiveLowInputpinusedtostopthePCICLK
clocks in an active low state. It will not effect PCICLK_F nor any
other outputs. This input pin only valid when MODE=0 (Power
ManagementMode)
CPUCLK(0:4)
These Output pins are the Clock Outputs that drive processor and
other CPU related circuitry that requires clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of these
ClocksarecontrolledbytheVoltagelevelappliedtotheVDDL2pin
of the device. See the FunctionalityTable for a list of the specific
frequencies that are available for these Clocks and the selection
codes to produce them.
I2C
TheSDATAandSCLOCKInputsareusetoprogramthedevice. The
clock generator is a slave-receiver device in the I2C protocol. It will
allow read-back of the registers. See configuration map for register
functions. The I2C specification in Philips I2C Peripherals Data
Handbook (1996) should be followed.
SDRAM(0:15)
TheseOutputClocksareusetodriveDynamicRAM’sandarelow
skew copies of the CPU Clocks. The voltage swing of the
SDRAM’soutputiscontrolledbythesupplyvoltagethatisapplied
to VDD3 of the device, operates at 3.3 volts.
IOAPIC(0:2)
These Outputs are fixed frequency Output Clocks that run at the
ReferenceInput(typically14.31818MHz). Itsvoltagelevelswing
is controlled by VDDL1 and may operate at 2.5 or 3.3volts.
4
ICS9150-01
General I2C serial interface information
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D2(H)
Then Byte 0, 1, 2, etc in
sequence until STOP.
+ 8 bits dummy
command code
+ 8 bits dummy
Byte count
ACK
ACK
ACK
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4protocol.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
ACK
Byte 0
ACK
Byte 1
ACK
Byte 0, 1, 2, etc in sequence until STOP.
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintainallpriorprogramminginformation.
H.
At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmaps
Byte 0: Functional and Frequency Select Clock Register (default = 0)
BIT
Bit 7
Bit 6
PIN#
DESCRIPTION
PWD
0
0
-
-
-
Reserved
Must be 0 for normal operation
Must be 0 for normal operation
In Spread Spectrum, Controls type
(0=centered, 1=down spread)
Bit 5
0
-
-
Must be 0 for normal operation
In Spread Spectrum, Controls Controls
Bit 4
0
-
Spreading %
(0=1.8%, 1=0.6%)
Bit 3
Bit 2
-
-
Reserved
Reserved
0
0
Bit1
Bit0
1
1 - Tri-State
0
0
Note: PWD=Power-UpDefault
Bit 1
Bit 0
-
1
0 - Spread Spectrum Enable
1 - Testmode
0 - Normal operation
I2C is a trademark of Philips Corporation
0
0
5
ICS9150-01
Select Functions
OUTPUTS
SDRAM
FUNCTION
DESCRIPTION
PCI,
PCI_F
CPU
REF
IOAPIC
Tri - State
Test Mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TCLK/21
TCLK/41
TCLK/21
TCLK1
TCLK1
Notes:
1. REF is a test clock on the X1 inputs during test mode.
Byte 1: CPU Clock Register
Byte 2: PCICLK Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
46
48
49
51
52
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
CPUCLK4 (Act/Inact)
CPUCLK3 (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
8
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
16
14
13
12
11
9
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4: SDRAM Clock Register
Byte 3: SDRAM Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7 (Act/Inact)
BIT
Bit 7
Bit 6
PIN#
24
25
PWD
1
1
DESCRIPTION
SDRAM15 (Act/Inact)
SDRAM14 (Act/Inact)
SDRAM13 (Act/Inact)
Desktop Only
SDRAM12 (Act/Inact)
Desktop Only
SDRAM11 (Act/Inact)
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
35
36
38
39
41
42
44
45
1
1
1
1
1
1
1
1
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit 5
Bit 4
32
33
1
1
Bit 3
Bit 2
Bit 1
Bit 0
18
19
21
22
1
1
1
1
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
6
ICS9150-01
Byte6:OptionalRegisterforFuture
Byte 5: Peripheral Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
2
54
55
-
-
-
3
PWD
DESCRIPTION
Reserved
IOAPIC2 (Act/Inact)
IOAPIC1 (Act/Inact)
IOAPIC0 (Act/Inact)
Reserved
Reserved
Reserved
REF0 (Act/Inact)
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
Notes:
Notes: 1 = Enabled; 0 = Disabled, outputs held low
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Power Management
Clock Enable Configuration
Other Clocks,
SDRAM,
REF,
IOAPICs
CPU_STOP# PCI_STOP#
CPUCLK
PCICLK
Crystal
VCOs
0
0
1
1
0
1
0
1
Low
Low
66.6/60 MHz
66.6/60 MHz
Low
33.3/30 MHz
Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
33.3/30 MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock
pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing
and signal loading may have a large impact on the initial clock distortion also.
ICS9150-01 Power Management Requirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1 (Enabled)1
1
1
1
1
CPU_ STOP#
PCI_STOP#
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
7
ICS9150-01
CPU_STOP#Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9150-01. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is
100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than
4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs
inside the ICS9150-01.
3. All other clocks continue to run undisturbed.
4. PCI_STOP# is shown in a high (true) state.
8
ICS9150-01
PCI_STOP#Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9150-01. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9150-01 internally. The minimum that the PCICLK (0:5) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:5) clocks. PCICLK (0:5) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9150 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9150.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
9
ICS9150-01
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
A
µ
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
75
IDD3.3OP CL = 0 pF; Select @ 66M
95
25
mA
Supply Current
Outputs Disabled
IDD3.3OE CL = 0 pF; With input address to Vdd or GND
18
36
mA
Supply Current
Input Capacitance1
CIN
CINX
Ttrans
Ts
Logic Inputs
5
45
3
pF
pF
ms
ms
ms
ps
X1 & X2 pins
27
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
5
5
TSTAB
3
500
4
TCPU-SDRAM2 VT = 1.5 V
200
2
Skew1
TCPU-PCI2 VT = 1.5 V
TREF-IOAPIC VT = 1.5 V
1
ns
900
ps
10
ICS9150-01
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
MIN
6
TYP
8
MAX UNITS
IDD2.5OP CL = 0 pF; Select @ 66M
9.5
mA
Supply Current
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads
250
2
500
4
ps
ns
ps
Skew1
TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads
TREF-IOAPIC VT = 1.5 V; VTL = 1.25 V; CPU Leads
1
860
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
15
TYP
MAX UNITS
1
Output Impedance
RDSP2B
VO = VDD*(0.5)
45
45
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN2B
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
15
2
Ω
VOH2B
VOL2B
IOH2B
IOL2B
2.6
0.3
-25
26
V
0.4
-16
V
mA
mA
VOL = 0.7 V
19
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.7
1.5
50
2
2
ns
ns
%
1
tf2 B
1
dt2B
55
1
tsk2B
VT = 1.25 V
60
250
250
150
+250
ps
ps
ps
ps
1
tjcyc-cyc2B VT = 1.25 V
150
30
1
Jitter
tj1s2B
VT = 1.25 V
VT = 1.25 V
1
tjabs2B
-250
80
1Guarenteed by design, not 100% tested in production.
11
ICS9150-01
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Output Impedance
RDSP4B
VO = VDD*(0.5)
30
30
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN4B
VO = VDD*(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
10
2
Ω
VOH4\B
VOL4B
IOH4B
IOL4B
2.4
0.45
-25
26
V
0.5
-16
V
mA
mA
19
40
1
Rise Time
Fall Time
tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.2
1.6
1.6
60
ns
ns
%
ps
ps
ps
1
tf4 B
1
Duty Cycle
dt4B
54
1
tjcyc-cyc4B VT = 1.25 V
1400
300
800
1
Jitter
tj1s4B
VT = 1.25 V
VT = 1.25 V
400
1
tjabs4B
-1000
1000
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
RDSP7
RDSN7
VOH7
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
24
24
Ω
10
Ω
2.6
2.75
0.3
-62
50
V
VOL7
0.4
-54
V
IOH7
mA
mA
IOL7
VOL = 0.8 V
42
40
1
Rise Time
Fall Time
Tr7
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.9
0.9
2
2
ns
ns
%
ps
ps
ps
1
Tf7
1
Duty Cycle
Dt7
54
60
1
tjcyc-cyc7B VT = 1.25 V
1400
350
900
1
Jitter
tj1s7B
VT = 1.25 V
VT = 1.25 V
1
tjabs7B
-1000
1000
1Guarenteed by design, not 100% tested in production.
12
ICS9150-01
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
MAX UNITS
1
Output Impedance
RDSP1
VO = VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VO = VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
Ω
VOH1
VOL1
IOH1
IOL1
2.6
3.1
0.15
-65
54
V
0.4
-54
V
mA
mA
40
45
1
Rise Time
Fall Time
Duty Cycle
Skew
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
50
2
ns
ns
%
ps
ps
ps
1
tf1
2
1
dt1
55
1
tsk1
VT = 1.5 V
200
10
500
150
250
1
Jitter
tj1s1
VT = 1.5 V
1
tjabs1
VT = 1.5 V
-250
65
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Output Impedance
RDSP3
VO = VDD*(0.5)
24
24
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
10
Ω
VOH3
VOL3
IOH3
IOL3
2.6
2.8
0.3
-67
55
V
0.4
-54
V
mA
mA
40
45
1
Rise Time
Fall Time
Duty Cycle
Skew
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
50
2
ns
ns
%
ps
ps
ps
1
Tf3
2
1
Dt3
55
1
Tsk3
VT = 1.5 V
200
50
500
150
250
1
Jitter
Tj1s3
VT = 1.5 V
1
Tjabs3
VT = 1.5 V
-250
100
1Guarenteed by design, not 100% tested in production.
13
ICS9150-01
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
α
A1
VARIATIONS
- CC --
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
18.31
MAX
18.55
MIN
.720
MAX
.730
56
.10 (.004)
C
R ef erence D oc.: J E D E C P ublicat ion 95, M O-118
10-00 3 4
300 mil SSOP Package
Ordering Information
ICS9150F-01
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
14
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