ICS9155-02W28L [ICSI]
Low Cost 20-Pin Frequency Generator; 低成本的20引脚，频率发生器
| 型号： | ICS9155-02W28L |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Cost 20-Pin Frequency Generator |
| 文件： | 总11页 (文件大小：390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AV9155
Integrated
Circuit
Systems, Inc.
Low Cost 20-Pin Frequency Generator
General Description
Features
The AV9155 is a low cost frequency generator designed spe-
cifically for desktop and notebook PC applications. Its CPU
clocks provide all necessary CPU frequencies for 286, 386 and
486 systems, including support for the latest speeds of proces-
sors. The device uses a 14.318 MHz crystal to generate the
CPU and all peripheral clocks for integrated desktop
motherboards.
Compatible with 286, 386, and 486 CPUs
Supports turbo modes
Generates communications clock, keyboard clock,
floppy disk clock, system reference clock, bus clock
and CPU clock
Output enable tristates outputs
Up to 100 MHz at 5V or 3.3V
20-pin DIP or SOIC
All loop filter components internal
Skew-controlled 2X and 1X CPU clocks
Power-down option
The dual 14.318 MHz clock outputs allows one output for the
system and one to be the input to an ICS graphics frequency
generator such as the AV9194.
The CPU clock offers the unique feature of smooth, glitch-free
transitions from one frequency to the next, making this ideal
device to use whenever slowing the CPU speed. The AV9155
makes a gradual transition between frequencies, so that it
obeys the Intel cycle-to-cycle timing specification for 486
systems. The simultaneous 2X and 1X CPU clocks offer
controlled skew to within 1.5ns (max) of each other.
ICS has been shipping motherboard frequency generators
sinceApril 1990, and is the leader in the area of multiple output
clocks on a single chip. The AV9155 is a third generation
device, and uses ICSs patented analog CMOS phase-locked
loop technology for low phase jitter. ICS offers a broad family
of frequency generators for motherboards, graphics and other
applications, including cost-effective versions with only one
or two output clocks. Consult ICS for all of your clock
generation needs.
ICSoffersseveralversionsoftheAV9155.Thedifferentdevices
are shown below:
PART
DESCRIPTION
AV9155C-01 Motherboard clock generator with 16 MHz BUS CLK
AV9155C-02 Motherboard clock generator with 32 MHz BUS CLK
AV9155C-23 Includes Pentium frequencies
AV9155C-36 Features a special 40 MHz SCSI clock
Block Diagram
Pentium is a trademark of Intel Corporation.
9155 Rev B 8/24/98
AV9155
Pin Configuration
20-Pin DIP or SOIC
20-Pin DIP or SOIC
Pin Descriptions for AV 9155-01, 9155-02
PIN
NUMBER
PIN NAME
TYPE
DESCRIPTION
1
2
1.843 MHz
Output
Output
Input
-
1.84 MHz clock output.
Crystal connection.
Crystal connection.
X2
3
X1
4
VDD
Digital power supply (3.3V or 5.0V).
Digital Ground.
5
GN D
-
6
16 MHz/32 MHz
24 MHz
12 MHz
AGND
O E
Output
Output
Output
-
16 MHz (-01) or 32 MHz (-02) clock output.
24 MHz floppy disk/combination I/O clock output.
12 MHz keyboard clock output.
7
8
9
Analog ground (original version).
10
11
12
13
14
15
16
17
18
19
20
Input
Input
Input
Output
Output
-
O utput enable. Tristates all outputs when low. (Has internal pull-up.)
CPU clock frequency select #2. (Has internal pull-up.)
Power-down. Shuts off entire chip when low. (Has internal pull-up.)
14.318 MHz reference clock output.
14.318 MHz reference clock output.
Digital ground.
FS2
PD#
14.318 MHz
14.318 MHz
GND
VDD
-
Digital power supply (3.3V or 5.0V).
2X CPU clock output.
2XCPU
CPU
Output
Output
Input
Input
1X CPU clock output.
FS1
CPU clock frequency select #1. (Has internal pull-up.)
CPU clock frequency select #0. (Has internal pull-up.)
FS0
2
AV9155
Functionality - AV9155-01
(Using 14.318 MHz input.All frequencies in MHz.)
PERIPHERAL CLOCKS
CLOCK#2CPUand2XCPU
COMMCLK
(Pin 1)
BUSCLK
(Pin 6)
FDCLK
(Pin 7)
KBCLK
(Pin 8)
FS2
(Pin 11)
FS1
(Pin 19)
FS0
(Pin 20)
2XCPU
(Pin 17)
CPU
(Pin 18)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
32
40
50
66.66
80*
100*
4
8
16
20
25
33.33
40*
50*
1.843*
16*
24*
12*
REFERENCE CLOCKS
REFCLK1
(Pin 13)
REFCLK2
(Pin 14)
14.318
14.318
*5Vonly.
Functionality - AV9155-02
(Using 14.318 MHz input.All frequencies in MHz.)
PERIPHERAL CLOCKS
CLOCK#2CPUand2XCPU
COMMCLK
(Pin 1)
BUSCLK
(Pin 6)
FDCLK
(Pin 7)
KBCLK
(Pin 8)
FS2
(Pin 11)
FS1
(Pin 19)
FS0
(Pin 20)
2XCPU
(Pin 17)
CPU
(Pin 18)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
32
40
50
66.66
80*
100*
4
8
16
20
25
33.33
40*
50*
1.843*
32*
24*
12*
REFERENCE CLOCKS
REFCLK1
(Pin 13)
REFCLK2
(Pin 14)
14.318
14.318
*5Vonly.
Frequency Transitions
Using an Input Clock as Reference
A key feature of the AV9155 is its ability to provide smooth,
glitch-freefrequencytransitionsontheCPUand2XCPUclocks
when the frequency select pins are changed. These frequency
transitions do not violate the Intel 486 specification of less
than 0.1% frequency change per clock period.
The AV9155 is designed to accept a 14.318 MHz crystal as the
input reference. With some external changes, it is possible to
use a crystal oscillator or clock input. Please see application
note AN04 for details on driving the AV9155 with a clock.
3
AV9155
Pin Configuration
20-Pin DIP or SOIC
20-Pin DIP or SOIC
Pin Descriptions for AV9155-23, -36
PIN
NUMBER
PIN
NAME
TYPE
DESCRIPTION
1
2
1.843/40 MHz
X2
Output
Output
Input
-
1.84 MHz (-23)/40 MHz SCSI (-36) clock output.
Crystal connection.
3
X1
Crystal connection.
4
VDD
Digital power supply (+5V)
5
GND
-
Digital ground.
6
16 MHz/15 MHz
24 MHz
12 MHz
AGND
OE
Output
Output
Output
-
16 MHz (-23)/15 MHz (-36) clock output.
24 MHz floppy disk/combination I/O clock output.
12 MHz keyboard clock output.
7
8
9
Analog ground (original version).
10
11
12
13
14
15
16
17
18
19
20
Input
Input
Input
Output
Output
-
Output enable. Tristates all outputs when low. (Has internal pull-up.)
CPU clock frequency select #2. (-23 has internal pull-up.)
Power-down. Shuts off entire chip when low. (Has internal pull-up.)
14.318 MHz reference clock output.
14.318 MHz reference clock output.
Digital ground.
FS2
PD#
14.318 MHz
14.318 MHz
GND
VDD
-
Digital power supply (3.3V or 5.0V).
2X CPU clock output.
2XCPU
CPU
Output
Output
Input
Input
1X CPU clock output.
FS1
CPU clock frequency select #1. (-23 has internal pull-up.)
CPU clock frequency select #0. (-23 has internal pull-up.)
FS0
4
AV9155
Functionality - AV9155-23
(Using 14.318 MHz input.All frequencies in MHz.)
CLOCK#2CPUand2XCPU
PERIPHERAL CLOCKS
FS2
(Pin 11)
FS1
(Pin 19)
FS0
(Pin 20)
2XCPU
(Pin 17)
CPU
(Pin 18)
COMMCLK
(Pin 1)
BUSCLK
(Pin 6)
FDCLK
(Pin 7)
KBCLK
(Pin 8)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75*
32
37.5*
16
1.843
16*
24
12
60
30
40
50
66.66
80*
52
20
25
33.33
40*
26
REFERENCE CLOCKS
REFCLK1
(Pin 13)
REFCLK2
(Pin 14)
14.318
14.318
*5Vonly
Functionality - AV9155-36
(Using 14.318 MHz input.All frequencies in MHz.)
CLOCK#2CPUand2XCPU
PERIPHERAL CLOCKS
SCSICLK
(Pin 1)
BUSCLK
(Pin 6)
FDCLK
(Pin 7)
KBCLK
(Pin 8)
FS2
(Pin 11)
FS1
(Pin 19)
FS0
(Pin 20)
2XCPU
(Pin 17)
CPU
(Pin 18)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
16
60
40
50
66.66
80*
100*
4
8
30
20
25
33.33
40*
50*
40*
15*
24*
12*
REFERENCE CLOCKS
REFCLK1
(Pin 13)
REFCLK2
(Pin 14)
14.318
14.318
*5Vonly
5
AV9155
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5VtoVDD +0.5V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics at 5V
V
DD = 4.0 to 5.5V (5V +10%/-20%); TA=0°C to 70°C unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
VIL
TEST CONDiTIONS
VDD=5V
MIN
TYP
MAX
0.8
UNITS
V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Output High Voltage
Output High Voltage
Supply Current
VIH
VDD=5V
2.0
V
ILL
VIN=0V
-1 5uA
µA
µA
V
IIH
VIN=VDD
5
VOL
VOH
VOH
VOH
Icc
IOL=4mA
0.4
IOH=-lnlA, VDD=5.OV
IOH=-4nIA, VDD=5.OV
I H=-8mA
No load1
VDD-.4V
VDD-.8V
2.4
V
V
V
40
80
mA
Supply Current, Power-Down
ICDSTBY
No load
0.7
1.5
mA
Output Frequency Changeover
Supply and Temperature
Short circuit current
Pull-up resistor value
Input Capacitance
FD
With respect to typical frequency
Each output clock
0.002
0.01
%
Isc
Rpu
Ci
25
40
680
mA
k
Ω
Except Xl, X2
Pins Xl, X2
10
p
Load Capacitance
CL
20
AC Characteristics
25pF load
25pF load
25pF load
25pF load
Output Rise time, 0.8 to 2.0V
Rise time, 20% to 80% VDD
Output Fall time, 2.0 to 0.8V
Fall time, 80% to 20% VDD
Duty cycle
tr
tr
tr
-
-
-
-
1
2
1
2
4
2
ns
ns
ns
ns
%
%
%
tf
2
4
dt
dt
fji1s
25pF load
25pF load
40/60
40/60
48/52
43/57
0.8
60/40
60/40
2.5
Duty cycle, reference clocks
Jitter, one sigma
As compared with clock period
Jitter, absolute
tjab
tjab
fi
16-100 MHz clocks
2
5
%
ps
Jitter, absolute
700
Input Frequency
Clock skew between CPUand
2XCPU outputs
14.318
0.5
MHz
Tsk
tft
1
ns
Frequency Transition time
From 8 to 100 MHz
15
20
ms
Notes:
1All clocks onAV9155-xx running at highest possible frequencies. Power supply current can change substantially with different
mask configurations. Consult ICS.
6
AV9155
Actual Output Frequencies
(Using 14.318 MHz input. All frequencies in MHz.)
AV9155-01 andAV9155-02
CLOCK#2 CPU and 2XCPU
AV9155-23
CPUCLOCK
FS2
(Pin 11)
FS1
(Pin 19)
FS0
(Pin 20)
2XCPU
(Pin 17)
CPU
(Pin 18)
FS2
(Pin 11)
FS1
(Pin 19)
FS0
(Pin 20)
2XCPU
(Pin 17)
CPU
(Pin 18)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7.50
15.51
32.22
40.09
50.11
66.82
80.18*
100.23*
3.75
7.76
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
75.170*
31.940
60.136
40.090
50.113
66.476
80.181*
51.903*
37.585*
15.970
30.068
20.045
25.057
33.238
40.091*
25.952*
16.11
20.05
25.06
33.41
40.09*
50.11*
*5Vonly.
*5Vonly.
PERIPHERAL CLOCKS
PERIPHERAL CLOCKS
COMMCLK
(Pin 1)
BUSCLK (Pin
6)
FDCLK
(Pin 7)
KBCLK
(Pin 8)
COMMCLK
(Pin 1)
BUSCLK
(Pin 6)
FDCLK
(Pin 7)
KBCLK
(Pin 8)
1.846
32.01 or 16.00
24.00
12.00
1.846
16.00
24.00
12.00
AV9155-36
CPUCLOCK
FS2
FS1
FS0
2XCPU
CPU
(Pin 11)
(Pin 19)
(Pin 20)
(Pin 17)
(Pin 18)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.054
16.002
59.875
39.886
50.113
66.476
80.181*
100.226*
4.027
8.001
29.936
19.943
25.057
33.238
40.091*
50.113*
PERIPHERAL CLOCKS
COMMCLK
(Pin 1)
BUSCLK
(Pin 7)
FDCLK
(Pin 6)
KBCLK
(Pin 8)
40.00
15.00
24.00
12.00
7
AV9155
AV9155 Recommended External Circuit
Notes:
1. ICS recommends the use of an isolated ground plane for the AV9155. All grounds shown on this drawing should be
connected to this ground plane. This ground plane should be connected to the system ground plane at a single point. Please
refer to AV9155Board Layout Diagram.
2. A single power supply connection for all VDD lines at the 2.2µF decoupling capacitor is recommended to reduce interaction
of analog and digital circuits. The 0.1µF decoupling capacitors should be located as close to each VDD pin as possible.
3. A 33Ω series termination resistor should be used on any clock output which drives more than one load or drives a long trace
(more than about two inches), especially when using high frequencies (>50 MHz). This termination resistor is put in series with
the clock output line close to the clock output. It helps improve jitter performance and reduce EMI by damping standing waves
caused by impedance mismatches in the output clock circuit trace.
4. The ferrite bead does not enhance the performance of the AV9155, but will reduce EMI radiation from the VDD line.
8
AV9155
AV9155 Recommended Board Layout
This is the recommended layout for the AV9155 to maximize clock performance. Shown are the power and ground connections,
the ground plane, and the input/output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise
from propagating through the device. When compared to using the system ground and power planes, this technique will
minimize output clock jitter. The isolated ground plane should be connected to the system ground plane at one point, near the
2.2µF decoupling cap. For lowest jitter performance, this isolated ground plane should be kept away from clock output pins and
traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between the
isolated ground plane and system ground plane to preventAC coupling. The ferrite bead in the VDD line optional, but will help
reduce EMI.
The traces to distribute the output clocks should be over a system ground or power supply plane. The trace width should be
about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help minimize clock
jitter and EMI radiation. The traces to distribute power should be as wide as possible.
9
AV9155
20-Pin DIP Package
Ordering Information
AV9155-01N20, AV9155-02N20,
AV9155-23N20, AV9155-36N20
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3 SOIC or .6 DIP; None=Standard Width
Package Type
N=DIP (Plastic#)
T&R=Tape and Reel
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
Notes:
Tape and reel packaging should be ordered with the suffix T&R. For instance, if the -01 in DIPand tape & reel is required, order
thepartasAV9155-01CN20T&R.
10
AV9155
LEAD COUNT
DIMENSION L
14L
16L
18L
20L
24L
28L
32L
0.804
0.354
0.404
0.454
0.504
0.604
0.704
Ordering Information
AV9155-01W20, AV9155-02M20,
AV9155-23M20, AV9155-36M20
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3 SOIC or .6 DIP; None=Standard Width
Package Type
W=SOIC
T&R=Tape and Reel
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device
11
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