ICS9169C-40 [ICSI]
System Clock Chip; 系统时钟芯片型号: | ICS9169C-40 |
厂家: | INTEGRATED CIRCUIT SOLUTION INC |
描述: | System Clock Chip |
文件: | 总6页 (文件大小:331K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9169C-40
System Clock Chip
General Description
Features
8 selectable CPU clocks up to 75MHz
Six synchronous PCI clocks
The ICS9169C-40 is a Clock Synthesizer chip for Pentium or
Cyrix CPU based motherboards using PCI.
OneReferanceClockat14.318MHz
Power-up stabilization time = 2ms on all CPU and PCI
clocks, which meets Intel PentiumPro power-up
Low CPU and PCI clock jitter <500ps
Low skew output
Improved output drivers are designed for low EMI
Test Mode
Optional common or mixed supply mode:
Features include eight CPU clocks and six PCI clocks. A
Reference Output is available equal to the crystal frequency.
The device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up.
The ICS9169C-40 clock output are designed for low EMI
emissions. Controlled rise and fall times, unique output
driver circuits and innovative circuit layout techniques enable
the ICS9169C-40 to have lower EMI than other clock
devices.
(VDD=VDDL1=VDDL2=3.3V)
(VDD=3.3V,VDDL1=VDDL2=2.5)
(VDD=3.3V,VDDL1=3.3V,VDDL2=2.5V)
Space saving and low cost 34-pin SSOP package
The ICS9169C-40 accepts a 14.318MHz reference crystal or
clock as its input and runs from a 3.3V supply.
Pin Configuration
Block Diagram
34-Pin SSOP
FS2
0
FS1
0
FS0
0
CPU
50MHz
55MHz
REF/2
PCI
33.3MHz
36.67MHz
REF/4
0
0
1
0
1
0
0
1
1
75MHz
50MHz
55MHz
60MHz
66.6MHz
37.5MHz
25MHz
Functionality
1
0
0
3.3V±10%,0-70°C
1
0
1
27.6MHz
30MHz
Crystal (X1, X2) = 14.31818 MHz
1
1
0
1
1
1
33.3MHz
Pentium is a trademark on Intel Corporation.
9169C-40RevA072897P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS169C-40
Pin Descriptions
PIN NUMBER
PIN NAME
VDD
TYPE
PWR
OUT
PWR
-
DESCRIPTION
1, 9
Power supply
2
REF
Buffered output reference. 3.3V
Digital Ground.
3, 5, 18, 26, 32
4
GND
N/C
Not connected.
6, 7, 8, 10, 11, 12
13, 19, 20
PCI (1:6)
FS (0:2)
OUT
IN
Clock outputs - controlled by 3.3V V
DD
Frequency select inputs, these inputs have internal pull-ups.
Input for tristate. If PD# = 0, then all outputs are tristated and
the device is in shutdown mode (VCO’s off, crystal oscillator
is off and all logic is reset) When PD# = 1, the device is in
normal operating mode. Has internal pull-up
14
PD#
IN
15
AGND
N/C
PWR
-
Analog Ground
16
Not connected
17
AVDD
VDDL1
CPU (1:8)
VDDL2
X2
PWR
PWR
OUT
PWR
OUT
IN
Analog Power Supply
3.3/2.5V Power Supply for CPU (1:4)
Clock outputs.
21
22, 23, 24, 25, 27, 28, 29, 30
31
33
34
3.3/2.5V Power Supply for CPU (5:8)
Reference oscillator
X1
Reference oscillator
2
ICS169C-40
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7V, TA = 0 70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
SYMBOL
TEST CONDITIONS
MIN
-
TYP
-
MAX
UNITS
V
V
IL
IH
IL
0.2V
-
DD
V
0.7V
-
V
DD
I
VIN=0V
VIN=V
-50.0
-5.0
-
25.0
-
50
µA
µA
V
I
IH
5.0
0.4
-
DD
1
V
OL
V
OH
V
OL
V
OH
V
OL
IOL=12mA; for CPU, PCI
IOH=-12mA; for CPU, PCI
IOL=7.5mA; for Ref CLK
IOH=-15mA; for Ref CLK
0.3
2.8
0.3
2.8
1
Output High Voltage
2.4
-
V
1
Output Low Voltage
0.4
-
V
1
Output High Voltage
2.4
V
IOL=7.5mA: CPU only;
VDDL (1:2) = 2.5V
1
Output Low Voltage
-
0.3
0.4
V
V
IOH=-13mA; CPU only;
VDDL (1:2) = 2.5V
OH
DD
1
Output High Voltage
Supply Current
2.0
2.2
35
-
V
I
@66.6 MHz; all outputs unloaded
-
-
65
mA
µA
PD#=0
All Logic Inputs to VDD
244
500
Power Down Current
I
(PD)
DD
Other
-
371
700
µA
All Logic Inputs to GND
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
3
ICS169C-40
Electrical Characteristics at 3.3V
VDD = 3.0 3.7V, TA = 0 70°C unless otherwise stated
AC Characteristics
SYMBOL TEST CONDITIONS
PARAMETER
MIN
TYP
0.9
0.8
1.5
1.4
50
49
50
-
MAX
1.4
1.2
2.0
2.0
55
UNITS
ns
15pF load, 0.4 to 2.0V; VDD=VDDL
for All Outputs
15pF load, 2.0 to 0.4V; VDD=VDDL
for All Outputs
1
Rise Time
Tr1
Tf1
-
-
1
Fall Time
ns
15pF load, 0.4 to 2.0V; VDDL=2.5V &
VDD = 2.3V; CPU
1
Rise Time
Tr2
-
ns
15pF load, 2.0 to 0.4V; VDDL=2.5V &
VDD = 3.3V; CPU
1
Fall Time
Tf2
-
ns
15pF load CPU, PCI, REF @
VOUT=1.5V
1
Duty Cycle
Dt
45
45
-
%
15pF load; VDDL (1:2)=2.5V
VTH=1.25V
1
Duty Cycle
Dt
55
%
CPU & PCI Clocks; Load=15pF,
VDD=VDDL
CPU & PCI Clocks; Load=15pF,
VDD=VDDL
1
1
Jitter, One Sigma
Tj1s1
Tjab1
Tj1s2
Tjab2
150
220
300
500
+400
350
250
400
16.0
-
ps
1
Jitter, Absolute
-220
-
ps
Jitter, One Sigma
Ref; Load=15pF
200
-
ps
1
Jitter, Absolute
Ref Load=15pF
-500
-400
-350
-250
400
12.0
-
ps
VDD=VDDL; @ 60MHz
VDD=VDDL; @ 66MHz
VDD=VDDL; @ 75MHz
-
ps
-
ps
Jitter, Cycle to Cycle
(for CPU only)
T
CC
-
ps
VDD=3.3V; VDDL=2.5;
for All Frequencies
-
ps
1
Input Frequency
Fi
14.318
5
MHz
pF
pF
ms
ms
ps
1
1
Logic Input Capacitance
Crystal Oscillator
CIN
CINX
ton
Logic input pins
X1, X2 pins
-
18
2.5
1.8
14.5
2.0
-
1
Capacitance
From VDD=1.6V to 1st crossing of 66.6
MHz VDD supply ramp < 40ms
From 1st crossing of acquisition to <
1% settling
1
Power-on Time
-
4.5
2.0
250
4.0
Frequency Settling Time
ts
-
CPU to CPU & PCI to PCI; Load=15pF;
@1.5V
CPU to PCI; Load=15pF; @1.5V;
VDD=VDDL; CPU is early
CPU to PCI; Load=15pF; (CPU is early)
VDDL=2.5V, VTH=1.25V;
VDD=3.3V, VTH=1.5V
1
Clock Skew Window
Tsk1
Tsk2
-250
1.0
1
Clock Skew
ns
1
Clock Skew
Tsk3
0.50
1.5
3.0
ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS169C-40
Technical Pin Function Descriptions
VDD/AVDD
FS0, FS1, FS2
This is the power supply to the internal logic of the device as
well as the following clock output buffers:
These pins control the frequency of the clocks at the CPU,
PCI pins. See the Funtionality table at the beginning of this
data sheet for a list of the specific frequencies, and the
selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up. If a
"1" value is desired for a specific frequency selection bit,a
10K ohm restor must be connected from the apporapriate FS
pin to theVDD supply. If a "0" value is desired, then the 10K
resistor must be connected to ground.
PCI(1:6)
REF
This pin may be operated at any voltage between 3.0 and 5.5
volts. Clocks from the listed buffers that it supplies will
have a voltage swing from ground to this level. For the
actual guaranteed high and lowvoltage levels of these clocks,
please consult the AC parameter table in this data sheet.
REF
This is a fixed frequency clock that runs at the same frequency
as the input reference clock (typically 14.31818 MHz) is and
typically used to driveVideo and ISABUS requirements.
GND/AGND
This is the power supply ground return pin for the chip.
XIN
This pin serves one of two functions. When the device is
used with a crystal, XIN acts as the input pinfor the reference
signal that comes from the discrete crystal. When the device
is driven by an external clock signal, XIN is the device
input pin for that reference clock. This pin also implements
an internal crystal loading capacitor that is connected to
ground. See the data tables for the value of the capacitor.
VDDL(1:2)
This is the power supply to the CPU clock drivers. This pin
may be operated "at any voltage" between 2.5 and 3.3 volts.
Clocks from the buffers that it supplies will have a voltage
swing form ground to this level. For the actual guaranteed
high and low voltage levels of these clocks. Please consult
the AC parameter table in this data sheet.
XOUT
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode ofoperation, XOUT
is an output signal that drives (or excites) the discrete crystal.
This pin also implements aninternal crystal loading capacitor
that is connected to ground. See the data tables for the value
of the capacitor.
CPU(1:8)
These pins are the clock outputs that drive processor and
other CPU related circuitry that require clocks which are in
tight skew tolerance with the CPU clock. The voltage swing
of these clocks is controlled by that which is applied to the
VDDL (1:2) pin of the device. See the Functionality table at
the beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
PCI(1:6)
Outputs for PCI bus with a skew≤ 250pS.A high current rate
of 60mAis available at 3.3V. These outputs are supplied from
VDD.
5
ICS169C-40
SSOPPackage
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.097
.005
.090
.014
.0091
NOM.
.101
.009
.092
.016
MAX.
.104
.0115
.094
.019
.0125
MIN.
.701
NOM. MAX.
.706 .711
A
A1
A2
B
AA
34
C
.010
D
E
See Variations
.296
.292
.299
e
.040 BSC
H
h
L
.400
.010
.024
.406
.013
.032
.410
.016
.040
N
See Variations
5°
0°
8°
X
.085
.093
.100
Dimensions are in Inches
Ordering Information
ICS9169CF-40
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
PackageType
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
6
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