ICS9169CF-26 [IDT]
Processor Specific Clock Generator, 100MHz, PDSO36, SSOP-36;
| 型号： | ICS9169CF-26 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 100MHz, PDSO36, SSOP-36 光电二极管 |
| 文件： | 总5页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9169C-26
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator and Integrated Buffers
General Description
Features
Twelve selectable CPU clocks operate up to 83.3 MHZ
The ICS9169C-26 is a low-cost frequency generator
designe specifically for Pentium-based chip set systems.
The integrated buffer minimizes skew and provides all the
clocks required. A 14.318 MHz XTAL oscillator provides
the reference clock to generate standard Pentium
frequencies. The CPU clock makes gradual frequency
transitions without violating the PLL timing of internal
microprocessor clock multipliers.
Eight selectable CPU clocks operate up to100 MHz
Maximum CPU jitter of ±200ps
Seven BUS clocks support sync or async bus operation
500ps skew window for all synchronous clock edges
CPU clocks to BUS clocks in sync mode skew
1-4ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range
36-pin SSOP package
Either synchronous (CPU/2) or asynchronous (32 MHz)
PCI bus operation can be selected.
48 MHz clock for USB support and 24 MHz clock for FD
Block Diagram
Pin Configuration
36-Pin SSOP
CPU
(1:8)
MHz
BUS
REF
(1:3)
BSEL FS2
FS1 FS0
(0:7) 48 MHz 24 MHz
MHz
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
55
80
27.5
40
48
48
48
48
48
48
48
24
24
24
24
24
24
24
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Functionality
100
75
50
3.3V±10%, 0-70°C
37.5
25
Crystal (X1, X2) = 14.31818 MHz
50
66.6
60
33.3
30.0
Tristate Tristate Tristate Tristate Tristate
48 24 14.318
select select select Tristate 32.0
Pentium is a trademark on Intel Corporation.
9169C-26RevB091997P
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS169C-26
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 7, 13, 27, 33
VDD
PWR
Power for control logic, PLL and output buffers.
XTAL or external reference frequency input. This input
includes XTAL load capacitance and feedback bias for a 12 -
16 MHz crystal, nominally 14.31818 Mhz.
2
X1
IN
3
X2
OUT
PWR
XTAL output which includes XTAL load capacitance.
4, 10, 16, 23, 30
GND
Ground for logic, PLL and output buffers.
Processor clock outputs which are a multiple of the input
reference frequency as shown in the table above.
Frequency multiplier select pins. See table above. These inputs
have internal pull-up devices.
5, 6, 8, 9, 11, 12, 14, 15
17, 18, 19
CPU(1:8)
FS(1:2)
OUT
IN
20
BSEL
BUS(1:7)
48MHz
24MHz
IN
Selector for synchronous or asynchronous bus operation.
21, 22, 24, 25, 26, 28, 29
OUT
OUT
OUT
Bus clock outputs.
31
32
Fixed 48 MHz clock (with 14.318 MHz input).
Fixed 24 MHz clock (with 14.318 MHz input).
REF is a buffered copy of the crystal oscillator or reference
input clock, nominally 14.31818 Mhz.
34, 35, 36
REF(1:3)
OUT
2
ICS169C-26
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5V to VDD +0.5V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conitions for extended
periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 3.7V, TA = 0 70°C unless otherisstated
DC Characteristics
PARAMETER
SYMBOL
VIL
TEST CONDITIONS
MIN
TYP
-
MAX
UNITS
V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Current1
Output High Current1
Output Low Current1
Output High Current1
Output Low Voltage1
Output High Voltage1
Output Low Voltage1
Output High Voltage1
Supply Current
-
0.2VDD
VIH
IIL
0.7VDD
-
-
-
V
VIN=0V
-28.0
-10.5
-
µA
µA
mA
mA
mA
mA
V
IIH
VIN=VDD
-5.0
5.0
-
IOL
VOL=0.8V; for CPUs & BUSes
VOL=2.0V; for CPUs & BUSes
VOL=0.8V; for fixed CLKs
VOL=2.0V; for fixed CLKs
IOL=15mA; for CPUs & BUSes
IOH=-30mA; for CPUs & BUSes
IOL=12.5mA; for fixed CLKs
IOH=-20mA; for fixed CLKs
@66.6 MHz; all outputs unloaded
30.0
47.0
-66.0
38.0
-47.0
0.3
2.8
0.3
2.8
55
IOH
-
-42.0
-
IOL
25.0
IOH
-
-
-30.0
0.4
-
VOL
VOH
VOL
VOH
IDD
2.4
-
V
0.4
-
V
2.4
-
V
110
mA
Note 1: Parameter is guaradesign and characterization. Not 00% tested in production.
3
ICS169C-26
Preliminary Product Preview
Electrical Characteristics at 3.3V
VDD = 3.0 3.7V, TA = 0 70°C unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
0.9
0.8
1.5
1.4
50
MAX
1.5
1.4
2.5
2.4
55
UNITS
ns
20pF load, 0.8 to 2.0V
CPU & BUS
Rise Time1
Tr1
-
20pF load, 2.0 to 0.8V
CPU & BUS
Fall Time1
Tf1
-
ns
20pF load, 20% to 80%
CPU & BUS
Rise Time1
Tr2
-
ns
20pF load, 80% to 20%
CPU & BUS
Fall Time1
Tf2
-
ns
Duty Cycle1
Dt
20pF load @ VOUT=1.4V
45
%
CPU & BUS Clocks;
Jitter, One Sigma1
Jitter, Absolute1
Jitter, One Sigma1
Jitter, Absolute1
Input Frequency1
Logic Input Capacitance1
Crystal Oscillator Capacitance1
Tj1s1
-
50
150
200
3
ps
Load=20pF, >25 MHz
PCLK & BCLK Clocks;
Load=20pF, FOUT>25 MHz
Tjab1
Tj1s2
Tjab2
Fi
-200
-
ps
Fixed CLK; Load=20pF
-
-5
12.0
-
1
%
Fixed CLK; Load=20pF
2
5
%
14.318
5
16.0
-
MHz
pF
pF
CIN
Logic input pins
X1, X2 pins
CINX
-
18
-
From VDD=1.6V to 1st crossing
of 66.6 MHz VDD supply
ramp < 40ms
Power-on Time1
ton
-
2.5
4.5
ms
From 1st crossing of
acquisition to < 1% settling
CPU to CPU;
Load=20pF; @1.4V
BUS to BUS;
Load=20pF; @1.4V
CPU & BUS;
Load=20pF; @1.4V
Frequency Settling Time1
Clock Skew1
ts
-
-
2.0
150
300
2.6
4.0
250
500
4
ms
ps
ps
ns
Tsk1
Tsk2
Tsk3
Clock Skew1
-
Clock Skew1
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
4
ICS169C-26
Preliminary Product Preview
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.097
.008
.090
.0091
.0091
NOM.
.101
.010
.092
.014
.010
MAX.
.110
.0116
.094
.017
MIN.
.602
.701
.620
.720
NOM. MAX.
A
A1
A2
B
AA
AB
AC
AD
.607
.706
.625
.725
612
.711
.630
.730
36
44
48
56
C
.0125
D
See Variations
E
.292
.296
.299
e
H
h
L
.0315 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
This table in inches
Ordering Information
ICS9169CF-26
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
PackageType
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
5
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