ICS9179-06 [ICSI]
Zero Delay Buffers; 零延迟缓冲器
| 型号： | ICS9179-06 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Zero Delay Buffers |
| 文件： | 总8页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9179-06
Zero Delay Buffers
General Description
Features
Zero delay buffer, 16 outputs
Supports up to four SDRAM DIMMS
Wide PLL loop bandwidth makes this part ideal in
Spread Spectrum applications.
Skew Input to FB_IN ±250ps default, with selectable
skew-2.7, +2.0, -0.7nsnominal.
The ICS9179-06 generates low skew clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro.An output enable is provided for testability.
The device is a buffer with low output to output skew. This is
a zero delay buffer device, using an internal PLL. This buffer
can be used for phase synchronization to a master clock. With
the wide PLL loop BW, this buffer is compatible to Spread
Spectrum input clocks from clock generator products such as
the ICS9148-27.
Synchronous clocks skew matched to 250ps window on
output.
33 to 133MHz input or output frequency.
I2C Serial Configuration interface to allow individual
clocks to be stopped, or selectable delays.
Multiple VDD, VSS pins for noise reduction
Slew rate 1.5V/ns into 30pF.
VDD=3.3±5%, 0to70°C
All outputs (0:15) tristate with OE low
(FB_OUT stays running).
The individual clock outputs are addressable through I2C to be
enabled, or stopped in a low state for reduced EMI when the
lines are not needed. The device defaults to zero-delay mode,
but can be programmed with I2C for selectable delays -2.7,
+2.0, -0.7 ns (nominal target values).
48-PinSSOPpackage
Block Diagram
Pin Configuration
Functionality
48-Pin SSOP
OUTPUT
(0:15)
OE#
FB_OUT
0
1
Hi-Z
1 X INPUT
1 X INPUT
1 X INPUT
PentiumPro is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9179-06RevF6/22/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9179-06
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Tri-states all outputs except FB_OUT when held LOW. Has internal
pull-up.2
2
OE
IN
5, 6, 9, 10
OUTPUT (0:3)
OUTPUT (4:7)
OUT
OUT
SDRAM Byte 0 clock outputs1
SDRAM Byte 1 clock outputs1
15, 16, 19, 20
29, 30, 33, 34
OUTPUT (8:11)
OUTPUT (12:15)
INPUT
OUT
OUT
IN
SDRAM Byte 2 clock outputs1
SDRAM Byte 3 clock outputs1
Input for reference clock.
Feedback input.
Data pin for I2C circuitry3
Clock pin for I2C circuitry3
Feedback output to input FB_IN.
40, 41, 44, 45
12
13
24
25
37
FB_IN
IN
SDATA
I/O
SCLK
I/O
FB_OUT
OUT
3, 7, 11, 17, 21, 31,
35, 38, 42, 46
4, 8, 14, 18, 28, 32,
36, 39, 43, 47
VDD
GND
PWR
PWR
3.3V Power supply for output buffers
Ground for output buffers
22
23
VDDA
VDDS
PWR
PWR
3.3V Power supply for Analog PLL stages
3.3V Power supply for I2C circuitry
26
27
GNDS
GNDA
N/C
PWR
PWR
-
Ground for I2C circuitry
Ground for Analog PLL stages
Pins are not internally connected
1, 48
Notes:
1.
2.
3.
At power up all sixteen outputs are enabled and active.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
completeplatformflexibility.
I2C Byte0, bits 0 & 1 used to select delay. Default* values at power up is 0
Subject to design engineering verification of target value.
4.
5.
Delay Selection Table4
Power Groups
VDD = Power supply for OUTPUT buffers
VDDS = Power supply for I2C circuitry
VDDA= Power supply forAnalog PLLcircuitry
5
INPUT
Control
Byte0 bit1
FB_IN
Control
Byte0 bit0
Nominal Target
Delay, INPUT to
FB_IN pins.
Ground Groups
GND = Ground supply for OUTPUT buffer
GNDS = Ground supply for I2C circuitry
GNDA= Ground supply forAnalog PLLcircuitry
0*
0
0*
1
0ns
-2.7ns
+2.0ns
-0.7ns
1
0
1
1
2
ICS9179-06
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
3
ICS9179-06
ICS9179-06 Power Management
The values below are estimates of target specifications.
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
Condition
All static inputs = VDD or GND
No Clock Mode
(BUF_IN - VDD1 or GND)
I2C Circuitry Active
30mA
Active 66MHz
(BUF_IN = 66.66MHz)
150mA
180mA
Active 100MHz
(BUF_IN = 100.00MHz)
Byte 2: OUTPUT Clock Register (Default = 1)
Byte 3: OUTPUT Clock Register
BIT PIN# PWD
DESCRIPTION
OUTPUT 15 (Act/Inact)
OUTPUT 14 (Act/Inact)
OUTPUT 13 (Act/Inact)
OUTPUT 12 (Act/Inact)
OUTPUT 11 (Act/Inact)
OUTPUT 10 (Act/Inact)
OUTPUT 9 (Active/Inactive)
OUTPUT 8 (Active/Inactive)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6 44
Bit 5 41
45
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 4 40
Bit 3 34
Bit 2
Bit 1 30
Bit 0 29
33
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Serial Configuration Command Bitmaps
Byte0:OUTPUTClockRegister(default=0)
Byte1:OUTPUTClockRegister
BIT PIN# PWD DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Reserved
Bit7
Bit6
Bit5
Bit4
20
19
16
15
10
9
1
1
1
1
1
1
OUTPUT 7 (Act/Inact)
OUTPUT 6 (Act/Inact)
OUTPUT 5 (Act/Inact)
OUTPUT 4 (Act/Inact)
OUTPUT 3 (Act/Inact)
OUTPUT 2 (Act/Inact)
OUTPUT 1 (Act/Inact)
OUTPUT 0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 12
Bit 02
-
-
0
0
0
0
0
0
0
0
Reserved
-
Reserved
-
Reserved
Bit3
Bit2
-
Reserved
-
Reserved
Bit1
Bit0
6
5
1
1
12
13
Clock INPUT Skew Control
FBIN Skew Control
Notes: 2 = Default = 0; 1 = Delay element enabled,
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
0 = No delay path.
4
ICS9179-06
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA =0- 70C; Supply Voltage VDD =3.3V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input LowVoltage
Input High Current
Input LowCurrent
Input LowCurrent
Operating
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IH
VDD+0.3
V
V
V
IL
VSS-0.3
0.8
5
IIH
IIL1
IIL2
IDD
V = VDD
uA
uA
uA
mA
mA
mA
mA
MHz
pF
IN
V =0 V; Inputs with no pull-up resistors
-5
IN
V =0 V; Inputs with pull-up resistors
-60
-33
115
170
IN
CL =0 pF; FIN @66M
CL =0 pF; FIN @100M
CL =0 pF; FIN @66M
CL =0 pF; FIN @100M
VDD =3.3 V; All Outputs Loaded
Logic Inputs
150
180
30
Supply Current
Output Disabled
Supply Current
IDD
30
Input frequency
F
i
33
105
5
CIN
Input Capacitance
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
uA
uA
uA
mA
mA
MHz
pF
IIL
-5
Input Low Current
IIL
VIN = 0 V; Inputs with 100K pull-up resistors -60
CL = 0 pF; FIN @ 66M
-33
115
170
Operating
IDD1
IDD2
Fi1
150
180
150
5
Supply Current
Input frequency
Input Capacitance
CL = 0 pF; FIN @ 100M
VDD = 3.3 V; All Outputs Loaded
Logic Inputs
10
1
CIN
1Guarenteed by design, not 100% tested in production.
5
ICS9179-06
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Frequency
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO3
CONDITIONS
MIN
33
TYP
MAX UNITS
133
24
MHz
Ohm
Ohm
V
RDSP3
RDSN3
VOH3
VOL3
IOH3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
10
10
24
2.6
0.4
-54
V
mA
mA
nS
IOL3
VOL = 0.8 V
40
45
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.33
1.33
55
Fall Time
Duty Cycle
Tf3
nS
Dt3
%
Output to Output
Skew Window
Tsk3
VT = 1.5 V
250
250
pS
pS
VT = 1.5 V default Zero delay I2C
B0 bits 0, 1 = 00
Tskd1
-250
0
IN to FB_IN Skew1, 2
Tskd2
Tskd3
Tskd4
VT = 1.5 V bits 0, 1 = 10
VT = 1.5 V bits 0, 1 = 01
VT = 1.5 V bits 0, 1 = 11
-2.2
+1.5
-0.2
-2.7
+2.0
-0.7
-3.2
+2.5
-1.2
nS
nS
nS
Notes:
1. Guarenteed by design, not 100% tested in production
2. Delay elements FBIN and clock INPUT path are selected by I2C BYTE2; bit 0 = clock input control, bit 1 = Clock INPUT
Control. (Default is 0). A0 = No delay in path, 1 = Delay element selected.
Note: PWD = Power-Up Default
Input Pulse
MIN
1.0
TYP
MAX UNITS
ns
Input Pulse
Low Time
Tim-Low
Vpulse_Low ≤ 0.8V
Vpulse_High ≥ 2.0V
Input Pulse
High Time
Tim-High
1.5
ns
6
ICS9179-06
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
CapacitorValues:
All unmarked capacitors are 0.01µF ceramic
7
ICS9179-06
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
MIN. NOM. MAX.
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
A
A1
A2
B
AC
.620
.625
.630
48
C
D
E
See Variations
.296
.292
.299
e
H
h
L
N
0.025 BSC
.406
.013
.032
See Variations
.400
.010
.024
.410
.016
.040
0°
.085
5°
.093
8°
.100
X
Ordering Information
ICS9179F-06
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
8
information being relied upon by the customer is current and accurate.
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