ICS9179BF-01 [ICSI]
Low Skew Buffers; 低偏移缓冲器
| 型号： | ICS9179BF-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Skew Buffers |
| 文件： | 总9页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9179B-01
Low Skew Buffers
General Description
Features
High speed, low noise non-inverting (0:17) buffer for
SDRAM clock buffer applications.
Supports up to four SDRAM DIMMS
Synchronous clocks skew matched to 250ps window on
SDRAM.
The ICS9179B-01 generates SDRAM clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro or Pentium II.An output enable is provided
for testability.
The device is a buffer with low output to output skew. This is
a Fanout buffer device, not using an internal PLL. This buffer
can also be a feedback to an external PLL stage for phase
synchronization to a master clock.
I2C Serial Configuration interface to allow individual
clocks to be stopped.
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
Custom configurations available
3.0V 3.7V supply range
48-pinSSOPpackage
The individual clock outputs are addressable through I2C to
be enabled, or stopped in a low state for reduced EMI when
the lines are not needed.
Block Diagram
Pin Configuration
48-Pin SSOP
PentiumProisatrademarkofIntelCorporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
9179B-01RevC05/18/98
ICS9179B-01
Pin Descriptions
PIN NUMBER
4, 5, 8, 9
PIN NAME
SDRAM (0:3)
SDRAM (4:7)
TYPE DESCRIPTION
OUT SDRAM Byte 0 clock outputs1
OUT SDRAM Byte 1 clock outputs1
OUT SDRAM Byte 2 clock outputs1
OUT SDRAM Byte 3 clock outputs1
13, 14, 17, 18
31, 32, 35, 36
40, 41, 44, 45
SDRAM (8:11)
SDRAM (12:15)
SDRAM (16:17)
BUF_IN
21, 28
11
OUT SDRAM clock outputs useable for feedback.1
IN
IN
Input for buffers
38
OE
Tri-states all outputs when held LOW. Has internal pull-up.2
Data pin for I2C circuitry3
24
25
SDATA
SCLK
I/O
I/O
Clock pin for I2C circuitry3
3, 7, 12, 16, 20,
VDD
GND
PWR 3.3V Power supply for SDRAM buffer
29, 33, 37, 42, 46
6, 10, 15, 19, 22,
27, 30, 34, 39, 43
PWR Ground for SDRAM buffer
23
26
VDDS
GNDS
N/C
PWR 3.3V Power supply for I2C circuitry
PWR Ground for I2C circuitry
1, 2, 47, 48
-
Pins are not internally connected
Notes:
1.
2.
3.
At power up all eighteen SDRAM outputs are enabled and active.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
completeplatformflexibility.
Power Groups
VDD = Power supply for SDRAM buffer
VDDS = Power supply for I2C circuitry
Ground Groups
GND = Ground for SDRAM buffer
GNDS=GroundforI2C circuitry
2
ICS9179B-01
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for SDRAM(0:17).
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
SDRAM(0:17)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing of
the SDRAMs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specificationinPhilipsI2CPeripheralsDataHandbook(1996)
should be followed.
BUF_IN
Input for Fanout buffers (SDRAM 0:17).
OE
OE tristates all outputs when held low.
VDDS
This is the power supply to I2C circuitry.
GNDS
This is the ground to I2C circuitry.
3
ICS9179B-01
General I2C serial interface information
A.
For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence, with
an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
Then Byte 0, 1, 2, etc in
sequence until STOP.
+ 8 bits dummy
command code
+ 8 bits dummy
Byte count
ACK
ACK
ACK
A(6:0) & R/W#
D2(H)
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4protocol.
Clock Generator
Address (7 bits)
Byte 0
ACK
Byte 1
ACK
ACK
Byte 0, 1, 2, etc in sequence until STOP.
A(6:0) & R/W#
D3(H)
C.
D.
E.
F.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches
maintain all prior programming information.
H.
At power-on, all registers are set to a default condition. Bytes 0 through 2 default to a 1 (Enabled output state).
Serial Configuration Command Bitmaps
Byte 0: SDRAM Clock Register
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PIN#
18
17
14
13
9
PWD
DESCRIPTION
1
1
1
1
1
1
1
1
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
8
5
4
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
4
ICS9179B-01
Functionality
OE#
SDRAM (0:3)
Hi-Z
SDRAM (4:7)
Hi-Z
SDRAM (8:11)
Hi-Z
SDRAM (12:15) SDRAM (16:17)
0
1
Hi-Z
Hi-Z
1 X BUF_IN
1 X BUF_IN
1 X BUF_IN
1 X BUF_IN
1 X BUF_IN
Byte 1: SDRAM Clock Register
Byte 2: PCICLK Clock Register
BIT
PIN# PWD
DESCRIPTION
SDRAM17 (Act/Inact)
SDRAM16 (Act/Inact)
Reserved
BIT
PIN#
45
PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
21
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM15 (Act/Inact)
SDRAM14 (Act/Inact)
SDRAM13 (Act/Inact)
SDRAM12 (Act/Inact)
SDRAM11 (Act/Inact))
SDRAM10 (Act/Inact)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact))
44
41
-
Reserved
40
-
Reserved
36
35
-
Reserved
32
-
Reserved
31
-
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low
ICS9179B-01 Power Management
The values below are estimates of target specifications.
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
All static inputs = VDD or GND
Condition
No Clock Mode
(BUF_IN - VDD1 or GND)
3mA
I2C Circuitry Active
Active 66MHz
(BUF_IN = 66.66MHz)
115mA
180mA
Active 100MHz
(BUF_IN = 100.00MHz)
5
ICS9179B-01
Absolute Maximum Ratings
SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IH
VDD+0.3
V
V
V
IL
VSS-0.3
0.8
5
IIH
V = VDD
uA
uA
uA
mA
mA
mA
mA
µA
IN
IIL
V = 0 V; Inputs with no pull-up resistors
-5
IN
Input Low Current
IIL
V = 0 V; Inputs with 100K pull-up resistors
-60
-33
80
IN
IDD1
IDD2
IDD3
IDD4
IDD5
CL = 0 pF; FIN @ 66M
CL = 0 pF; FIN @ 100M
120
180
260
360
500
120
180
240
Operating Supply
Current
CL = 30 pF; RS=33 ; FIN @ 66M
Ω
CL = 30 pF; RS=33 ; FIN @ 100M
Ω
Stopped, input at 0 or VDD
VDD = 3.3 V; All Outputs Loaded
Logic Inputs
Fi1
10
150
5
MHz
pF
Input frequency
1
Input Capacitance
CIN
1Guaranteed by design, not 100% tested in production.
6
ICS9179B-01
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
RDSP
RDSN
VOH
CONDITIONS
MIN
10
TYP
MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -36 mA
IOL = 23 mA
VOH = 2.0 V
24
24
Ω
Ω
10
2.4
3
V
VOL
0.27
-115
57
0.4
-54
V
IOH
mA
mA
IOL
VOL = 0.8 V
40
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Tr
Tf
Dt
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.95
0.95
51
1.33
1.33
55
ns
ns
%
45
1
Tsk
VT = 1.5 V
VT = 1.5 V
110
5
250
6
ps
ns
TPROP
Propagation1
TPROPEN VT = 1.5 V
TPROPDIS VT = 1.5 V
1
1
8
8
ns
ns
1Guarenteed by design, not 100% tested in production.
7
ICS9179B-01
GeneralLayoutPrecautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
2) Make all power traces and vias as
wide as possible to lower
inductance.
Notes:
1 All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of
diagram
2 Optional EMI capacitor should be
used on all CPU, SDRAM, and PCI
outputs.
CapacitorValues:
All unmarked capacitors are 0.01µF ceramic
8
ICS9179B-01
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
.625 .630
A
A1
A2
B
AC
48
C
D
See Variations
E
.292
.296
.299
e
H
h
L
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9179BF-01
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS,AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
9
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