ICS9212YF-13LF [ICSI]
Direct Rambus⑩ Clock Generator; 直接Rambus ™时钟发生器
| 型号： | ICS9212YF-13LF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Direct Rambus⑩ Clock Generator |
| 文件： | 总7页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9212-13
Integrated
Circuit
Systems, Inc.
Direct Rambus™ Clock Generator
General Description
Features
•
•
Compatible with all Direct Rambus™ based IC s
Up to 600 MHz differential clock source for direct
Rambus™ memory system
Cycle to cycle jitter is less than 40ps
3.3 + 5% supply
Synchronization flexibility: Supports Systems that
need clock domains of Rambus channel to
synchronize with system or processor clock, or
systems that do not require synchronization of the
Rambus clock to another system clock
The ICS9212-13 is a High-speed clock generator providing
up to 600 MHz differential clock source for direct Rambus™
memory system. It includes DDLL (Distributed Delay
locked loop) and phase detection mechanism to
synchronize the direct Rambus™ channel clock to an
external system clock. ICS9212-13 provides a solution for
a broad range of Direct Rambus memory applications.The
device works in conjunction with the ICS9250-09.
•
•
•
The ICS9212-13 power management support system
turns “off” the Rambus™ channel clock to minimize power
consumption for mobile and other power–sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions
between clock-off and clock–on states. In “power down”
mode it completely powers down for minimum power
dissipation.
•
•
Excellent power management support
REFCLK input is from the ICS9250-09.
The ICS9212-13meetstherequirementsforinputfrequency
tracking when the input frequency clock is using Spread
Spectrum clocking and also the optimum bandwidth is
maintained while attenuating the jitter of the reference
signal.
Block Diagram
BUSCLK_STOP#
Pin Configuration
VDDREF
REFCLK
VDD1
1
2
3
24
23
22
21
20
19
18
17
16
15
14
13
FS0
FS1
VDD-OUT
GND-OUT
BUSCLKT
N/C
PD#
FS(0:1)
Test MUX
GND1
4
Bypass MUX
GND3
5
GND
Bypclk
PCLK/M
SYNCLK/N
GND2
6
7
8
9
10
11
12
PLLclk
PLL
BUSCLKC
GND-OUT
VDD-OUT
MULTI0
MULTI1
FS2
Refclk
B
A
BUSCLKT
BUSCLKC
Phase
Aligner
VDD2
VDDPD
BUSCLK_STOP#
PD#
PAclk
GND
Phase
Detector
Multi(0:1)
2
Pclk/M
Synclk/N
24-Pin 150 Mil SSOP
0272F—08/08/07
ICS9212-13
Pin Descriptions
Pin #
Name
Type
Description
1
VDDREF
REFV
Reference voltage for refclk, to be connected to CK133
2
3
4
5
REFCLK
VDD1
GND1
IN
Reference clock, to be connected to CK133
3.3 V power supply used for PLL
Ground for PLL
PWR
PWR
PWR
GND3
Ground for control inputs
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Ground for phase aligner
3.3 V power supply used for phase aligner
Reference voltage for phase detector inputs connected
to the controller
6,7
PCLK/M, SYNCLK/N
IN
8
9
GND2
VDD2
PWR
PWR
10
11
12
VDDPD
BUSCLK_ STOP#
PD#
REFV
IN
Active low output enable/disable
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting
the multiply ratio for the PLL from the input REFCLK
3.3V supply for clock out puts
IN
14,15
MULTI (0:1)
IN
16
17
VDD_OUT
GND_OUT
PWR
PWR
Ground for clock outputs
Out put clock connected to the Rambus channel. This
output is the complement of BUSCLK
NOT USED
Output clock connected to the Rambus channel. This
output is the true component of BUSCLK
Ground for clock outputs
18
19
20
BUSCLKC
N/C
OUT
N/C
BUSCLKT
OUT
21
22
GND_OUT
VDD_OUT
PWR
PWR
3.3V supply for clock out puts
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
13,23,24
FS(0:2)
IN
0272F—08/08/07
2
ICS9212-13
PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B)
Multo
Mult1
A
4
6
16
8
B
1
1
3
1
PLLCLK for REFCLK=50MHz
PLLCLK for REFCLK=66.66MHz
0
0
1
1
0
1
0
1
Reserved
300
266.7
400
266.6
400.0
355.5
533.3
Bypass and Test Mode Selection
Mode
FS0
FS1
FS2
0
Bypclk (int.)
BusClk
BusClkB
Normal
0
0
Gnd
PAclk
PAclkB
Bypass
1
0
0
PLLclk
PLLclk
PLLclkB
Test
1
1
0
Refclk
Refclk
RefclkB
Vendor Test A
Vendor Test B
Reserved
0
0
1
-
-
-
-
-
-
1
0
1
-
-
-
-
1
1
1
Output Test (OE)
0
1
X
Hi-Z
Hi-Z
Power Management Modes
State
PwrDnB
StopB
NORMAL
Clk Off
Powerdown
1
1
0
1
0
X
0272F—08/08/07
3
ICS9212-13
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics-input/supply/Outputs
Parameters
Symbol
Min
Max
Unit
Supply Voltage
VDD
3.135
3.465
V
Refclk Input cycle time
Input cycle-to-cycle Jitter
tCYCLE,IN
tJ,IN
10
-
40
ns
ps
250
Input Duty cycle over 10k cycles
40%
30
60%
33
DCIN
Fm,in
tCYCLE
kHz
Input frequency of modulation
Modulation index
PM,IN
0.25
30
-0.5
25%
0.5
100
0.5
%
ns
tCYCLE,PD
tCYCLE,PD
Phase detector input cycle time at PDclk/M & Synclk/N
Initial phase error at phase detector inputs
Phase detector input duty cycle over 10k cycles
Input rise & fall times ( measured at 20%-80% of input voltage) for
PDCLK/M & SYNCLK/N,&REfCLK
tCYCLE,PD
Terr,init
DCIN,PD
75%
TIR,TIF
-
1
ns
Input capacitance at PDCLK/M,Synclk/N,&REFCLK
Input Capacitance matching at PCLK/M & SYNCLK/N
Input capacitance at CMOS pins
CIN,PD
DCIN,PD
CIN,CMOS
VIL
-
7
pF
pF
pF
-
-
-
0.5
10
0.3
-
Input (CMOS) signal low voltage
Vdd
Vdd
Vddi,R
Input (CMOS) signal high voltage
VIH
0.7
-
REFCLK input low voltage
VIL,R
0.3
REFCLK input high voltage
Input signal low voltage for PD inputs and STOP
VIH,R
0.7
-
-
Vddi,R
Vddi,PD
0.3
VIL,PD
VIH,PD
VDD,IR
VDDI,PD
Input signal high voltage for PD inputs and STOP
Input supply referance for REFCLK
0.7
1.3
1.3
-
Vddi,PD
3.465
3.465
V
V
Input supply referance vfor PD inputs
Phase detector phase error for distributed loop measured at
PDCLK/M & SYNCLK/N(rising
tERR,PD
-100
100
ps
Cycle cycle time
tCYCLE
2.5
3.75
40
ns
ps
ps
Cycle-to-cycle jitter at Busclk/BUSCLKB (533 MHz)
Total jitter over 1 - 6 cycles (533MHz)
tJ
tJ
-
-
30
Phase aligner, phase step size (BSCLK/BUSCLKB)
PLL out put phase error when tracking SSC
tSTEP
1
-
ps
ps
tERR,SSC
-100
100
Out put crossing-point voltage
Output voltage swing
VX
1.3
0.4
1.8
0.6
V
V
VCOS
Output high voltage
VH
-
40%
-
2
V
tCYCLE
ps
Out put duty cycle over 10k cycle
DC
60%
50
Output cycle -to-cycle duty cycle error
tDC,ERR
tCR,tCF
tCR,CF
IDD
Output rise & fall times ( measured at 20%-80% of output voltage)
Difference between rise and fall times on a single device(20%-80%)
300
-
500
100
ps
ps
Opearting Supply Current
150
mA
0272F—08/08/07
4
ICS9212-13
Recommended Layout
General Layout Precautions:
1) Use a ground plane on the top layer of
the PCB in all areas not used by traces.
2) Make all power traces and vias as wide
as possible to lower inductance.
Capacitor Values:
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
0272F—08/08/07
5
ICS9212-13
COMMON
DIMENSIONS
VARIATIONS
D
S
SYMBOL
MIN. NOM. MAX.
MIN. NOM. MAX. MIN. NOM. MAX.
N
A
A1
A2
B
.061
.004
.055
.008
.0075
.064
.006
.058
.010
.008
.068
.0098
.061
.012
.0098
AA
AB
AC
AD
.189
.337
.337
.386
.194
.342
.342
.391
.196
.344
.344
.393
.0020 .0045 .0076
.0500 .0525 .0550
.0250 .0275 .0300
.0250 .0280 .0300
16
20
24
28
C
D
E
e
H
L
SEE VARIATIONS
.150
.155
.025 BSC
.236
.157
150 mil SSOP Package
.230
.010
.244
.016
.013
N
S
SEE VARIATIONS
SEE VARIATIONS
Diminisions are in inches
0°
0.85
5°
0.93
8°
.100
∝
X
Ordering Information
ICS9212yF-13LF
Example:
ICS XXXX y F - PPLF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
0272F—08/08/07
6
ICS9212-13
Revision History
Rev.
Issue Date Description
Page #
F
08/08/07 Fixed typo on Electrical Characteristics.
4
0272F—08/08/07
7
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