ICS9214 [ICSI]
Rambus XDR Clock Generator; Rambus公司的XDR时钟发生器
| 型号： | ICS9214 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Rambus XDR Clock Generator |
| 文件： | 总16页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS9214
Systems, Inc.
RambusTM XDRTM Clock Generator
General Description
Features
•
•
400 – 500 MHz clock source
4 open-drain differential output drives with short term
jitter < 40ps
Spread spectrum compatible
Reference clock is differential or single-ended, 100 or
133 MHz
The ICS9214 clock generator provides the necessary clock
signals to support the Rambus XDRTM memory subsystem
and Redwood logic interface. The clock source is a reference
clock that may or may not be modulated for spread spectrum.
The ICS9214 provides 4 differential clock pairs in a space
saving 28-pin TSSOP package and provides an off-the-shelf
high-performance interface solution.
•
•
•
SMBus programmability for:
- frequency multiplier
- output enable
- operating mode
Supports frequency multipliers of: 3, 4, 5, 6, 8, 9/2,
15/2 and 15/4
Support systems where XDR subsystem is
asynchronous to other system clocks
2.5V power supply
Figure 1 shows the major components of the ICS9214 XDR
Clock Generator. These include the a PLL, a Bypass
Multiplexer and four differential output buffers. The outputs
can be disabled by a logic low on the OE pin. An output is
enabled by the combination of the OE pin being high, and 1
in its SMBus Output control register bit.
•
•
•
The PLL receives a reference clock, CLK_INT/C and outputs
a clock signal at a frequency equal to the input frequency
times a multiplier. Table 2 shows the multipliers selectable
via the SMBus interface. This clock signal is then fed to the
differential output buffers to drive the enabled clocks. Disabled
outputs are set to Hi-Z. The Bypass mode routes the input
clock, CLK_INT/C, directly to the differential output buffers,
bypassing the PLL.
Up to four ICS9214 devices can be cascaded on the same
SMBus. Table 3 shows the SMBus addressing and control for
the four devices.
Block Diagram
Pin Configuration
OE
AVDD2.5
AGND
IREFY
1
2
3
4
5
6
7
8
9
28 VDD2.5
OE
RegA
27 ODCLK_T0
26 ODCLK_C0
25 GND
24 ODCLK_T1
23 ODCLK_C1
22 VDD2.5
ODCLK_T0
BYPASS#/PLL
ODCLK_C0
AGND
Bypass
MUX
CLK_INT
CLK_INC
VDD2.5
GND
SMBCLK
SMBDAT 10
OE 11
OE
RegB
ODCLK_T1
ODCLK_C1
CLK_INT
CLK_INC
PLL
21 GND
OE
RegC
20 ODCLK_T2
19 ODCLK_C2
18 GND
ODCLK_T2
ODCLK_C2
SMB_A0 12
SMB_A1 13
BYPASS#/PLL 14
17 ODCLK_T3
16 ODCLK_C3
15 VDD2.5
SMBCLK
OE
RegD
ODCLK_T3
ODCLK_C3
28-Pin 4.4mm TSSOP
SMBDAT SMB_A0 SMB_A1
0809D–04/07/06
Integrated
Circuit
ICS9214
Systems, Inc.
Pin Descriptions
PIN #
1
2
PIN NAME
AVDD2.5
AGND
PIN TYPE
PWR
DESCRIPTION
2.5V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
PWR
This pin establishes the reference current for the differential
3
IREFY
OUT
clock pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current.
Analog Ground pin for Core PLL
"True" reference clock input.
"Complementary" reference clock input.
Power supply, nominal 2.5V
4
5
6
7
8
AGND
CLK_INT
CLK_INC
VDD2.5
GND
PWR
IN
IN
PWR
PWR
IN
Ground pin.
9
10
SMBCLK
SMBDAT
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active high input for enabling outputs.
I/O
11
OE
IN
0 = tri-state outputs, 1= enable outputs
12
13
SMB_A0
SMB_A1
IN
IN
SMBus address bit 0 (LSB)
SMBus address bit 1
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
14 BYPASS#/PLL
IN
15
16
VDD2.5
PWR
OUT
Power supply, nominal 2.5V
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
ODCLK_C3
17
18
19
ODCLK_T3
GND
OUT
PWR
OUT
ODCLK_C2
20
ODCLK_T2
IN
21
22
GND
VDD2.5
IN
PWR
Power supply, nominal 2.5V
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Ground pin.
"Complementary" side of open drain differential clock output.
This open drain output needs an external resistor network..
"True" side of open drain differential clock output. This open
drain output needs an external resistor network..
Power supply, nominal 2.5V
23
ODCLK_C1
OUT
24
25
26
ODCLK_T1
GND
OUT
PWR
OUT
ODCLK_C0
27
28
ODCLK_T0
VDD2.5
OUT
PWR
0809D—04/07/06
2
Integrated
Circuit
ICS9214
Systems, Inc.
General SMBus serial interface information for the ICS9214
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D8(H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D8(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D9(H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
Controller (Host)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D8(H)
Slave Address D8(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address D9(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0809D—04/07/06
3
Integrated
Circuit
ICS9214
Systems, Inc.
SMB Table: Output Control Register
Control
Function
Byte 0
Pin #
Name
Type
0
1
PWD1
-
Test Mode
MULT2
Reserved for Vendor
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Enable
0
0
0
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Multiplier Select
Multiplier Select
Multiplier Select
Output Control
Output Control
Output Control
Output Control
See Table 2.
-
-
MULT1
MULT0
ODCLK_T/C0
ODCLK_T/C1
ODCLK_T/C2
ODCLK_T/C3
27,26
24,23
20,19
17,16
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Disable = Output in high-impedance state
Enable = Output is switching
SMB Table: Frequency Multiplier Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 1
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
-
Disable
Enable
Test Mode
Reserved for Vendor
RW
0
Bit 0
SMB Table: Revision & Vendor ID Register
Control
Function
Byte 2
Pin #
Name
Type
0
1
PWD
-
-
-
-
RID4
RID3
RID2
RID1
RID0
VID2
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Revision ID
Vendor ID
VID1
VID0
R
R
-
-
-
-
0
1
Bit 1
Bit 0
NOTES:
1. PWD = Power Up Default
0809D—04/07/06
4
Integrated
Circuit
ICS9214
Systems, Inc.
PLL Multiplier
Table 2 shows the frequency multipliers in the PLL, selectable by programming the MULT0, MULT1 and MULT2 bits in the
SMBus Multiplier Control register. Power up default is 4.
Table 2. PLL Multiplier Selection
Byte 0
Output Frequency (MHz)
Frequency
Multiplier
CLK_INT/C =
100 MHz1
CLK_INT/C =
133 MHz1
Bit 6
Bit 5
Bit 4
MULT2
MULT1
MULT0
0
0
0
0
0
1
3
4
3003
4002
400
533
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
5
6
500
600
800
450
750
375
667
800
3
8
-
9/2
15/2
15/4
600
3
-
500
NOTES
1 Output frequencies are based on nominal input frequencies of 100 MHz and 133 MHz. The PLL
multipliers are also applicable to spread spectrum modulated input clocks.
2 Default muliplier value at power up
3 Outputs at these settings do not conform to the AC Output Characteristics, or are not supported.
4 Shaded areas are under development and are not yet supported
Device ID and SMBus Device Address
The device ID (SMB_A(1:0)) is part of the SMBus device address. The least significant bit of the address designates a write
or read operation. Table 3 shows the addresses for four ICS9214 devices on the same SMBus.
Table 3. SMBus Device Addresses
ICS9214
8-bit SMBus Device Address, Including Oper.
Device Operation
Hex Address
SMB_A1
SMB_A0
WR#/RD
Write
D8
D9
DA
DB
DC
DD
DE
0
1
0
1
0
1
0
0
0
0
Read
Write
1
0
1
1
1
0
1
Read
11011
Write
2
Read
Write
3
Read
DF
1
0809D—04/07/06
5
Integrated
Circuit
ICS9214
Systems, Inc.
Operating Modes
Table 4: Operating Modes
Byte 0
Byte 1
BYPASS#/
PLL
OE
ODCLK_T/C3 ODCLK_T/C2 ODCLK_T/C1 ODCLK_T/C0
L
X
X
L
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
Z
Z
Z
Reserved for Vendor Test
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
CLK_INT/C1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
CLK_INT/C
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
Z
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
Z
Z
Z
Z
Z
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
Z
Z
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
CLK_INT/C
Z
CLK_INT/C
CLK_INT/C
H
H
02
12 12 12 12
CLK_INT/C
Notes
1 Bypass Mode
2 Power up default mode
0809D—04/07/06
6
Integrated
Circuit
ICS9214
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
DC Characteristics - Inputs
TA = 0°C to +70°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
SYMBOL
DD2.5, AVDD
DD2.5, IVDD
MIN
TYP
MAX
2.625
125
UNITS
V
mA
PARAMETER
Supply Voltage
Supply Current
High-level input
voltage
CONDITIONS
V
I
2.375
VIHCLK
VILCLK
VIXCLK
0.6
-0.15
0.2
0.95
0.15
0.55
V
V
V
Low-level input
voltage
CLK_INT, CLK_INC
Crossing point voltage
Difference in crossing
point voltage
VIXCLK
VTH
0.15
0.5VDD2.5
2.625
V
V
V
Input threshold
voltage
0.35
High-level input
voltage for single-
ended CLK_IN
Low-level input
voltage for single-
ended CLK_IN
High-level input
voltage
Low-level input
voltage
High-level input
voltage - SMBus
Low-level input
voltage - SMBus
Singled-ended
CLK_IN1
VIHSE
VTH + 0.3
VILSE
VTH - 0.3
-0.15
V
OE, SMB_A0,
SMB_A1,
BYPASS#/PLL
VIH
VIL
1.4
-0.15
1.4
2.625
0.8
V
V
V
V
VIHSMB
VILSMB
3.4652
0.8
SMBCLK, SMBDAT
-0.15
Notes:
1 When using singled-ended clock input, VTH is supplied to CLK_INTC as shown in Figure 2.
Duty cycle of singled-ended CLK_IN is measured at VTH
2 This range of SMBus input high voltages allows the 9214 to co-exist with 3.3V, 2.5V and 1.8V
devices on the same SMBus.
0809D—04/07/06
7
Integrated
Circuit
ICS9214
Systems, Inc.
DC Characteristics - Outputs
TA = 0°C to +70°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Power within spec to
outputs within spec
SMBus or Mode Select
transition to outputs valid
and within spec
MIN
TYP
MAX
UNITS
ms
tPU
Power up latency
3
State transition latency1
tCO
VOX
3
ms
V
Differential output
crossing voltage
Output Voltage Swing
(peak-to-peak singled
ended)
Measured as shown in Fig.
0.9
1.1
350
3
Measured as shown in Fig.
3. Excludes over and
undershoot.
VCOS
300
mV
Measured at ODCLK_T/C
Absolute output low voltage
0.85
0.98
V
V
VOLABS
pins
Reference Voltage for
swing control current
Ratio of output low
current to reference
current at typical VDD2.5
VISET
VDD = 2.3V, VOUT = 1V
1.02
7.2
IREF is equal to VISET/RRC
.
IOL/IREF
6.8
45
7
-
Tolerance of RRC <=+/-1%.
Measured at ODCLK_T/C
pins with termination per
Figure 3.
Minimum current at
VOLABS
IOLABS
-
mA
Low-level output voltage
SMBus
Low-level output current
VOLSMB
IOLSMB
IOZ
IOL = 4 mA
-
6
-
0.4
-
V
VOL= 0.8 V
mA
µΑ
SMBus
Tristate output current
Differential clock output pins
50
Notes:
There is no output latency or glitches if a value is written to an output register.
that is the same as its current contents.
0809D—04/07/06
8
Integrated
Circuit
ICS9214
Systems, Inc.
AC Characteristics-Inputs
TA = 0°C to +70°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
CLK_INT/CLK_INC cycle time1
tCYCLEIN
7
11
ns
2
Cycle-to-Cycle Jitter
185
60
ps
%
t
cyc-tcyc
dtin
Input clock duty cycle
CLK_INT/CLK_INC rise and fall
time
40
over 10,000 cycles
20% to 80% of input
voltage
tR, tF
175
700
ps
Difference between input rise
and fall time on same pin of a
single device
20% to 80% of input
voltage
tR-F
-
150
ps
Spread spectrum modulation
frequency
3
30
33
0.6
kHz
%
fINM
Triangular modulation
Spread spectrum modulation
index
3
mINDEX
Non-triangular modulation
0.54
%
20% to 80% of input
voltage
CLK_INT, CLK_INC
VI = VDD2.5 or GND
Bypass Mode
tsl(I)
Input clock slew rate
1
4
V/ns
Input Capacitance5
Input Capacitance5
CLK_INT cycle time
SMBus clock frequency
Notes:
CINCLK
CIN
tCYCLETST
fSMB
7
10
40
pF
pF
ns
4
10
100
kHz
1. Measured at (VIH(nom) - VIL(nom))/2 and is the absolute value of the worst case deviation.
2. Measured at crossing points for differential clock input or at VTH for single-ended clock input
3. If input modulation is used. Input modulation is not necessary.
4. The amount of allowed spreading for non-triangular modulation is determined
by the induced downstream tracking skew.
5. Capacitance measured at f = 1 MHz, DC bias = 0.9V, VAC <100mV.
0809D—04/07/06
9
Integrated
Circuit
ICS9214
Systems, Inc.
AC Characteristics-Outputs
TA = 0°C to +70°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER1
Output clock cycle time
Short term jitter (over 1 to
6 clock cycles)
SYMBOL
tCYCLE
CONDITION
MIN
TYP
MAX UNITS
1.5
-
-
2.5
40
30
ns
ps
ps
f = 400 to 635 MHz
f = 635 to 800 MHz
tJ2
Output Phase error when
tracking SSC
tERR,SSC
-100
100
ps
ps
%
TA = 0°C to +70°C,
AVDD2.5, VDD2.5 =
2.5 V +/- 0.125V
3
Change in skew
-
15
tSKEW
Long term average output
duty cycle
DC
45
55
Cycle-to-cycle duty cycle
f = 400 to 635 MHz
f = 635 to 800 MHz
20% to 80% of output
voltage
-
-
40
30
ps
ps
tDCERR
error
tR, tF
Output rise and fall times
100
300
100
-
ps
ps
Ω
Difference between
output rise and fall time
on same pin of a single
device
20% to 80% of output
voltage, f = 400 to 800 MHz
tR-F
-
Dynamic output
4
VOL = 0.9 V
1000
ZOUT
impedance
Notes:
1. Max and min output clock cycle times are based on nominal output frequencies
of 400 and 667 MHz respectively. For spread spectrum modulated input clocks,
the output clocks track the input modulation.
2. Output short-term jitter is the absolute value fo the worst case deviation and is
defined in the Jitter section.
3. tSKEW is the timing difference between any two of the four differential clocks and
is measured at common mode voltage.
4. Zout is defined at the output pins.
5. Guaranteed by design and characterization, not 100% tested in production
Thermal Characteristics
Parameter
Symbol Conditions
Min.
Typ.
120
95
Max.
Units
Still air
θJA
θJA
θJA
θJC
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to
Ambient
1 m/s air flow
3 m/s air flow
80
Thermal Resistance Junction to Case
20
Thermal Resistance Junction to Top of
Case
Maximum Case Temp
ΨJT
Still Air
°C/W
°C
4.5
120
0809D—04/07/06
10
Integrated
Circuit
ICS9214
Systems, Inc.
Clock Output Drivers
Figure 2 shows the clock driver equivalent circuit. The differential driver produces a specified voltage swing on the channel
by switching the currents going into ODCLK_T and ODCLK_C. The external resistor RRC at the IREFY pin sets the maximum
current. The minimum current is zero.
The voltage at the IREFY pin, VIREFY, is by design equal to 1 V nominally, and the driver current is seven times the current
flowing through RRC. So, the output low current can be estimated as IOL = 7/ RRC
.
The driver output characteristics are defined together with the external resistors, R1, R2, and R3. The output clock signals are
specified at the measurement points indicated in Figure 2. Table 5 shows example values for the resistors.
R1, R2, and R3 and the clock driver output impedance, ZOUT, must match the impedance of the channel, ZCH , to minimize
secondary reflections. ZOUT is specified as 1000 Ohms, minimum to accomplish this. The effective impedance can be
estimated by:
(1000R1/(1000+R1)+R2) R3/(1000R1/(1000+R1)+R2+R3)
Pull-up resistor RT terminates the transmission line at the load to minimize clock signal reflection signal reflections. Table 5
shows the resistor values for establishing and effective source termination impedance of 49.2 Ohms to match a 50 Ohm
channel. The termination voltages are 2.5 V for VTS and 1.2 V for VT.The resistor values R1 = 38.3 Ohms, R2 = 19.1 Ohms, R3
= 54.9 Ohms and RRC = 200 Ohms can be used to match a 28 Ohm channel.
Table 5. Example Resistor Values and Termination Voltages for a 50 Ohm Channel1
Symbol
R1
Parameter
Value
39.2
66.5
93.1
49.9
200
Tolerance
+/- 1%
+/- 1%
+/- 1%
+/- 1%
+/- 1%
+/-5%
Unit
ꢀ
Termination resistor
Termination resistor
Termination resistor
Termination resistor
Swing control resistor
Source termination voltage
Termination voltage
R2
ꢀ
R3
ꢀ
RT
ꢀ
RRC
ꢀ
VTS
VT
2.5
V
1.2
+/-5%
V
Notes:
1 A different set of resistors is used in Figure 2 when testing
for maximum output current of the clock driver (IOLABS).
These resistors are: R1 = 34ꢀ, R2 = 31.8ꢀ, R3 = 48.7ꢀ,
RT=28ꢀ, RRC = 147ꢀ
Supply Voltage
VTH
CLK_INC
CLK_INT
Input
Input
CLK_INT
XDR
XDR
Clock Generator
Clock Generator
b. Single-ended input
a. Differential input
Figure 1. Differential and single-ended reference clock inputs
0809D—04/07/06
11
Integrated
Circuit
ICS9214
Systems, Inc.
Input Clock Signal
The ICS9214 receives either a differential or single-ended reference clock (CLK_INT/C). When the reference input clock is
from a differential clock source, it must meet the voltage levels and timing requirements listed in the DC Characteristics –
Inputs and AC Characteristics – Inputs tables.
For a singled-ended clock input, an external voltage divider and a supply voltage, as shown in Figure 2, provide a reference
voltage VTH at the CLK_INC pin to determine the proper switching point for CLK_INT. The range of VTH is specified in the DC
Characteristics – Inputs table.
Measurement
Point
VTS
R1
VT
RT
ODCLK_T
ZCH
R2
R3
Differential Driver
Swing Current
Control
Measurement
Point
VTS
VT
RT
R1
R2
ISET
ODCLK_C
ZCH
R
RC
R3
Figure 2. Example System Clock Driver Equivalent Circuit
VH
80%
V(t)
20%
VL
tF
tR
Figure 3. Input and OutputVoltageWaveforms
ODCLK_T
ODCLK_C
Vx+
Vx,nom
Vx-
Figure 4. Crossing-pointVoltage
0809D—04/07/06
12
Integrated
Circuit
ICS9214
Systems, Inc.
Power Sequencing
Supply voltages for the ICS9214 must be applied before, or at the same time and external input and output signals.
ODCLK_T
ODCLK_C
tCYCLE,i
tJ = tCYCLE,
tCYCLE,i+1
-
tCYCLE, i+1 over 10,000 consecutive cycles
Figure 5. Cycle-to-cycle Jitter
ODCLK_T
ODCLK_C
t4CYCLE, i+1
t4CYCLE i+1 over 10,000 consecutive cycles
t4CYCLE, i
tJ = t4CYCLE, i
-
Figure 6. Short-term Jitter
Cycle (i)
Cycle (i+1)
ODCLK_T
ODCLK_C
tPW- (i)
tPW+ (i)
tPW- (i+1)
tCYCLE (i+1)
tPW+ (i+1)
tCYCLE (i)
tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)
Figure 7. Cycle-to-cycle Duty Cycle Error
f
NOM
(1-P
)*f
M,IN NOM
0.5/f
1/f
M,IN
M,IN
t
Figure 8. Input frequency Modulation
0809D—04/07/06
13
Integrated
Circuit
ICS9214
Systems, Inc.
Phase Noise
The 9214 meets the single side band phase noise spectral purity for offset frequencies between 1 MHz and 100 MHz as
described by the equation:
10log[1+(50 x 106/f)2.4] -138 dBc/Hz
This equation is shown in Figure 9. Phase Noise Plot
-100
10 log[1 + ( 50x106/ f )2.4] -138
-110
( Upper Lim it )
-120
-130
-140
-150
6
7
8
9
10
10
10
10
Offset Frequency f , Hz
Figure 9 : Phase Noise Plot
Sample points are for this equation are shown in Table 6. Phase Noise Data Points
Offset
Frequency
(MHz)
1
5
10
15
20
40
80
100
SSB Spectral
Purity
-97
-114
-121
-125.2
-
-133.7
-136.8
-137.3
128
(dbc/Hz)
Table 6 : Phase Noise Data Points
0809D—04/07/06
14
Integrated
Circuit
ICS9214
Systems, Inc.
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SYMBOL
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
A
A1
A2
b
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
0.0256 BASIC
.018 .030
SEE VARIATIONS
.177
0.75
N
SEE VARIATIONS
α
0°
--
8°
0.10
0°
--
8°
.004
aaa
VARIATIONS
D mm.
D (inch)
N
MIN
9.60
MAX
9.80
MIN
.378
MAX
.386
28
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
Ordering Information
ICS9214yG LF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Annealed Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0809D—04/07/06
15
Integrated
Circuit
ICS9214
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
Updated SMBus table Byte 2, Bit 3 from:0 to:1.
Updated PLL Multiplier Selection Table, from: Byte 1 to: Byte 0, and Bit 2,1,0,
to: Bit 6,5,4.
0.1
3/30/2005
4-5,15
Updated Ordering Information from "Lead Free" to "Annealed Lead Free"
Added Phase noise spec
Removed unsupported speeds from PLL Multiplier Selection,
Changed minimum output raise, fall times from 140ps to 100 ps
A
B
4/6/2005 Compliant with Rev 0.81 of XCG spec.
1. Changed write address from D2 to a valid address (D8)
4/22/2005 2. Changed read address from D3 to a valid address (D9)
Various
3
C
D
11/11/2005 Added the 15/4 entry in the gear table to the list of supported frequencies
4/7/2006 Added Thermal Characteristics Table.
5
10
0809D—04/07/06
16
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