ICS9219YGLF-T [ICSI]
Direct Rambus Clock Generator Lite; 直接Rambus时钟发生器精简版
| 型号： | ICS9219YGLF-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Direct Rambus Clock Generator Lite |
| 文件： | 总8页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9219
Integrated
Circuit
Systems,Inc.
Direct Rambus™ Clock Generator Lite
General Description
Features
TM
•
•
Compatible with all Direct Rambus based ICs
ICS9219 is a High-speed clock generator providing 400 or
533 MHz differential clock source for direct Rambus
memory system. ICS9219 takes a crystal as an input
reference source, and produces the differential output
clock required for the Rambus channel. ICS9219 provides
a solution for a broad range of Direct Rambus memory
applications. ICS9219 can be used in single or dual
Rambus channels. An additional LVCMOS output, which
provides a reference clock at the crystal frequency for the
other system blocks is also included.
Provides differential clock source for direct
Rambus memory system with 1GHz data transfer
rate capability
•
•
•
•
Cycle to Cycle jitter is less than 100ps
3.3V + 4% supply
LVCMOS REF clock @ crystal frequency
Output edge rate control to minimize EMI
Block Diagram
Pin Configuration
FS0
VDDT 1
GND 2
X2 3
16 FS0*
15 VDD
14 GND
13 BUSCLKT
12 BUSCLKC
11 GND
10 VDD
9 FS2*
X1
Xtal
OSC
BUSCLKT
PLL
BUSCLKC
X2
X1 4
VDD 5
REF 6
GND 7
FS1* 8
REF
VDDT
FS1
FS2
Control
Logic
16-Pin 173 mil TSSOP
* Pins have 60K internal pull-up to VDD
Table 1. PLL Multiplier Selection and Output Frequency
BUSCLK1
FS0
0
Mult
16
400.00
21.332
1
533.30
Notes:
1 Output frequencies are based on 25MHz XTAL Input
multipliers are also applicable to spread spectrum modulated input clocks.
2 Default muliplier value at power up.
0931B—10/25/04
ICS9219
Pin Descriptions
PIN #
PIN NAME
VDDT
GND
X2
PIN TYPE
PWR/IN
PWR
OUT
DESCRIPTION
Power supply, nominal 3.3V/Test mode
Ground pin.
Crystal output (14MHz to 25MHz)
Crystal input (14MHz to 25MHz)
Power supply, nominal 3.3V
Reference of Input
1
2
3
4
5
6
7
8
X1
IN
PWR
OUT
PWR
IN
VDD
REF
GND
FS1*
Ground pin.
Frequency select pin.
Real-time frequency select pin with internal 120Kohm pull-up resistor (check
SMBus HW/SW setting for priority).
9
FS2*
IN
10
11
VDD
GND
PWR
PWR
Power supply, nominal 3.3V
Ground pin.
Output clock connected to the Rambus channel. This output is the complement
of BUSCLK.
Output clock connected to the Rambus channel. This output is the true
component of BUSCLK.
Ground pin.
12
13
BUSCLKC
BUSCLKT
OUT
OUT
14
15
16
GND
VDD
FS0*
PWR
PWR
IN
Power supply, nominal 3.3V
Frequency select pin.
* Pins have 60K internal pull-up to VDD
Table 2: Function Table
FS(2:0)
INPUT
VDDT
MODE
BUSCLKT
BUSCLKC
REF
MULT
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
16
NORMAL INPUT x MULT
BUSCLKC
BUSCLKC
BUSCLKC
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
21.33 NORMAL INPUT x MULT
16 NORMAL INPUT x MULT
21.33 NORMAL INPUT x MULT
-
-
-
-
-
-
1
BUSCLKC
X
X
X
X
X
X
TEST
TEST
TEST
TEST
TEST
TEST
BUSCLKT/2
BUSCLKT/4
X1
BUSCLKC/2
BUSCLKC/4
X1(INVERT)
X1(INVERT)
X1(INVERT)/2
X1(INVERT)/4
X1
X1/2
X1/4
0931B—10/25/04
2
ICS9219
Absolute Maximum Ratings over operating free-air temperature
Supply voltage range, V
or V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V
DD
DDT
Input voltage range,V , at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to V
+ 0.5 V
+ 0.5 V
I
DD
DD
Output voltage range, V , at any output terminal (BUSCLKT/C). . . . . . . . . . . . . . . . . . . .-0.5 V to V
O
ESD rating (MIL-STD 883C, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 kV, Machine Model >200 V
Operating free-air temperature range, T ˚C to 85˚C
0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65˚C to 150˚C
stg
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
Recommended Operating Conditions
MIN
3
NOM
3.3
MAX
3.6
UNIT
V
Supply voltage, VDD
Low-level input voltage, VIL
0.35 x VDD
FS (2:0)
FS (2:0)
FS (2:0)
V
High-level input voltage, VIH
Internal pullup resistance
0.65 x VDD
90
14.0625
BUSCLKT/C
REF
150
26
16
kΩ
MHz
Input frequency at crystal input
25
Low-level output current, IOL
High-level output current, IOH
mA
mA
10
BUSCLKT/C
REF
-16
-10
15
15
85
FS (2:0)
X1, X2
Input capacitance (CMOS), CL
Operating free-air temperature
pF
C
0
Timing Requirements
MIN
2.5
MAX
3.7
4
UNIT
ns
Clock cycle time, t(CYCLE)
Input slew rate, SR
0.5
V/ns
ms
State transition latency (VDDX or S0 to CLKs - normal mode), t(STL)
3
Crystal Specifications
MIN
14.0625
-15
MAX
26
15
100
10
1500
25.3
UNIT
MHz
ppm
Ω
ppm
µΩ
mH
MΩ
dB
Frequency
Frequency tolerance (at 25°C) ± 3°C)
Equivalent resistance (CL = 10 pF)
Temperature drift (-10°C to 75°C)
Drive level
Motional inductance
Insulation resistance
0.01
20.7
500
3
Spurious attenuation ratio (at frequency ±500 kHz)
Overtone spurious
8
dB
0931B—10/25/04
3
ICS9219
Electrical Characteristics over Recommended Operating Free-Air Temperature
PARAMETER
TEST CONDITIONS*
MIN
TYP**
MAX
UNIT
V
Differential crossing-point output
voltage
See Figures 1 and 2
VX
1.25
1.6
1.85
Peak-to-peak output voltage swing,
single ended
VCOS
VOH - VOL
See Figure 1
0.4
0.6
0.7
V
Input clamp voltage
VIK
RI
VDD = 3V
VDD = 3.3V
VDD = 3.3V
VDD = 3.6V
VDD = 3.6V
VDD = 3.6V
VDD = 3.6V
VDD = 3.6V
II = -18 mA
VI = VO
-1.2
V
k
Input resistance
X1, X2
X2
>50
VO = 2V
VI = VDD
VI = VDD
VO = 0V
VI = 0V
27
10
mA
High-level input
current
IIH
FS0
mA
FS1, FS2
X2
10
-5.7
-100
-50
2.1
mA
mA
Low-level input
current
IIL
FS0
-30
-10
FS1, FS2
VI = 0V
See Figure 1
High-level output
voltage
BUSCLKT/C,
REF
VDD
0.1V
2.2
1
-
VOH
V
VDD = min to max
VDD = 3V
IOH = -1 mA
IOH = -16 mA
2.5
See Figure 1
Low-level output
voltage
BUSCLKT/C,
REF
VOL
IOH
IOL
0.05
0.25
-50
-50
-15
69
0.1
0.5
-32
V
VDD = min to max
VDD = 3V
IOH = 1 mA
IOH = 16 mA
VO = 1V
VDD = 3.135V
VDD = 3.3V
High-level output
current
BUSCLKT/C,
REF
mA
mA
VO = 1.65V
VO = 3.135V
VO = 1.95V
VO = 1.65V
VO = 0.9V
-21
43
VDD = 3.465V
VDD = 3.135V
VDD = 3.3V
Low-level output
current
BUSCLKT/C,
REF
69
30
36
40
40
VDD = 3.465V
High-level dynamic output resistance4
Low-level dynamic output resistance4
rOH
rOL
IO - 14.5 mA to IO - 16.5 mA
IO - 14.5 mA to IO - 16.5 mA
12
12
25
17
BUSCLKT,
Output capacitance
CO
3
pF
BUSCLKC, REF
Static supply current
IDD
Outputs high or low (VDDT = 0V)
Outputs high or low (VDDT = 0V)
400 MHz
6.5
50
mA
mA
mA
mA
Static supply current
IDDL
84
91
100
120
IDD (NORMAL)
Supply current in normal state
533MHz
* VDD refers to any of the following: VDD, VDDT
.
** All typical values are at VDD = 3.3V, TA 25°C.
4
rO
=
VO/ IO. This is defined at the output terminals, not at the measurement point of figure 1.
0931B—10/25/04
4
ICS9219
Switching Characteristics over Recommended Operating Free-Air Temperature Range.
PARAMETER
TEST CONDITIONS*
MIN
TYP**
MAX
3.7
50
UNIT
t(CYCLE)
tJ
Clock cycle time (BUSCLKT/C)
1.8
ns
400 MHz
533 MHz
400 MHz
533 MHz
42
33
Total jitter over 1, 2, 3, 4, 5 or 6 clock
cycles
See Figure 3
ps
ps
50
300
300
53%
50
tJL
DC
Long-term jitter
See Figure 4
See Figure 5
See Figure 6
Output duty cycle over 10,000 cycles
43%
120
51
30
30
400 MHz
tDC,ERR
Output cycle-to-cycle duty cycle error
ps
ps
ps
533 MHz
50
Output rise and fall times (measured at
20%-80% of output voltage)
tCR, tDF
See Figure 7
See Figure 7
BUSCLKT/C
250
50
400
100
Difference between rise and fall times on a single
device (20% ± 80%) |tCR - tCF|
∆tRF
tCYCLE(L)
t(CJ)
t(CJ10)
DC(2)
Clock cycle time (REF)
REF cycle jitter
80
-0.2
142.2
0.2
ns
ns
ns
0.1
See Figure 8
Measured at 50%
REF 10-cycle jitter
-1.3 t(CJ)
47%
1.3 t(CJ)
53%
Output duty cycle
REF
REF
50
Output rise and fall times (measured at
20%-80% of output voltage)
tCRL, tCFL
See Figure 7
0.8
1
ns
fmod = 50 kHz
fmod = 8 MHz
-3
PLL loop bandwidth
dB
-20
0931B—10/25/04
5
ICS9219
Measurement Point
RT
RS
CF
ZCH
CMID
RP
RP
Differential Driver
CMID
RS
CF
RT
ZCH
Measurement Point
Figure 1. Example System Clock Driver Equivalent Circuit
CLK
Vx+
Vx,nom
Vx-
CLKB
Figure 2. Crossing-point Voltage
CLK
CLKB
t4CYCLE, i+1
t4CYCLE, i
tJ = 4CYCLE, i
t
-
t4CYCLE, i+1 over 10,000 consecutive cycles
Figure 3. Short-term jitter
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
tJ = CYCLE,i - tCYCLE, i+1 over 10,000 consecutive cycles
t
Figure 4. Cycle-to-cycle jitter
0931B—10/25/04
6
ICS9219
CLK
CLKB
tPW-
tCYCLE
DC = (tPW+ / tCYCLE
tPW+
)
Figure 5. Duty Cycle
Cycle (i)
Cycle (i+1)
CLK
CLKB
tPW- (i)
CYCLE (i)
tPW+ (i)
tPW- (i+1)
CYCLE (i+1)
tPW+ (i+1)
t
t
tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)
Figure 6. Cycle-to-cycle Duty Cycle Error
VH
80%
V(t)
20%
VL
tF
tR
Figure 7. Input and Output Voltage Waveforms
REF
T
Figure 8. REF Jitter
0931B—10/25/04
7
ICS9219
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
In Millimeters
(25.6 mil)
In Inches
c
N
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.19
0.09
MAX
1.20
0.15
1.05
0.30
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.012
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
6.40 BASIC
SEE VARIATIONS
0.252 BASIC
1
22
E1
e
L
4.30
0.65 BASIC
0.45
4.50
.169
0.0256 BASIC
.018
.177
α
D
0.75
.030
N
SEE VARIATIONS
SEE VARIATIONS
0°
--
8°
0.10
0°
--
8°
.004
α
aaa
A
A2
VARIATIONS
D mm.
D (inch)
A1
N
MIN
4.90
MAX
5.10
MIN
.193
MAX
.201
- CC --
16
e
SEATING
PLANE
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
b
aaa
C
Ordering Information
ICS9219yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0931B—10/25/04
8
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